A Comparison of Power Consumption in some CMOS Adder Circuits

D.J. Kinniment, J.D. Garside, B. Gao

Abstract

Addition is representative of many arithmetic processing operations that must be carried out in portable digital systems, and the speed and power consumption trade-offs in adder hardware are of interest to portable digital system designers.

In this paper we compare static and dynamic circuits, and synchronous and asynchronous architectures for speed, power per add and transistor count. Three adder circuits chosen for the comparison are: a synchronous static ripple carry adder, a static Manchester carry adder, and an asynchronous dynamic adder. The analysis and simulation results show that both the lowest power and best time-energy product per addition are given by the simple synchronous static adder based on the Manchester carry path.

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