Scan Testing of Micropipelines

O.A. Petlin, S.B. Furber,

Abstract

The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques.

Proc. 13th IEEE VLSI Test Symposium, Princeton, New Jersey, USA
May 1-3, 1995.