AMULET3i

AMULET3i is an asynchronous System-on-Chip macrocell designed within the OMI/ATOM project. First silicon was received in September 2000.

The macrocell contains the following blocks:

• An AMULET3 microprocessor
• 8 Kbytes of memory mapped RAM
• MARBLE - an on-chip asynchronous bus [REF]
• 16 Kbytes of ROM
• A DMA controller
• A flexible asynchronous interface to external memory
• A synchronous interface to on-chip peripherals

The picture above shows a chip plot of AMULET3i. The processor is on the right hand side and the eight 1Kbyte RAM blocks are clearly distinguishable at the bottom left.

This macrocell contains about 825,000 transistors (500,000 are within the RAM system) and measures 7.0 x 3.5mm in 0.35µm technology. Simulation suggested that the performance would be broadly equivalent to an ARM9 manufactured on an identical process (120MHz) in that instructions are executed at a rate between 100 and 140 million instructions per second (data dependent). Unfortunately the memory system on the first chip is a bottleneck, so that the speed simulating the Dhrystone 2.1 benchmark yields just over 100 (Vax) MIPS.

This version of AMULET3i was `taped out' in November 1999 as part of a telecoms controller chip known as DRACO. On DRACO, the AMULET3i is integrated with a large number of synchronous peripheral devices connected across a sync-async bridge. AMULET3i provides the computing resource for DRACO and its asynchronous operation contributes significantly to ensuring that the chip has low EMI.

Chips were received from the fab in September 2000 (yes, it took a while!) and were soon running the standard ARM Angel debug monitor on the test PCB. The standard C "Hello World" program ran very shortly thereafter and the chips were declared highly functional on 9/9/2000. The processor is capable of around 100 MIPS which is not quite as fast as the simulator had suggested but we have been unable to find out where the silicon is in relation to 'typical'. The MIPS/W rating of the processor core is around 620 - about the same as the ARM9.

Extensive testing of AMULET3i has revealed only two bugs and simple patches have been identified for both of these.

• Some inadequate drive transistors within the multiplier can cause multiplications to fail for certain operands.
• A logical oversight indicates a sequential cycle in one erroneous circumstance; this precludes the running of certain instructions from external DRAM.

In addition, a failure to inactivate parts of the multiplier under certain circumstances cost a power wastage of around 5%.

Exploitation

Unfortunately, the planned use of the DRACO device in a commercial product did not materialise and so AMULET3i has yet to find a real-world application. We still hope to find a suitable commercial application for AMULET3i, probably after porting it to a more up-to-date process, and we would welcome requests for collaboration in this area.

AMULET3i bibliography

• A Result Forwarding Mechanism for Asynchronous Pipelined Systems
• Memory Faults in Asynchronous Microprocessors
• AMULET3: A High-Performance Self-Timed ARM Microprocessor
• AMULET3 Revealed
• Asynchronous Macrocell Interconnect using MARBLE
• AMULET3i - an Asynchronous System-on-Chip

A slide presentation is also available.