A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.
O.A.Petlin, S.B.Furber, "Scan testing of asynchronous sequential circuits", Proc. 5th Great Lakes Symp. on VLSI, Buffalo, N.Y., USA, Mar. 16-18, 1995, pp. 224-229.
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The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques.
O.A.Petlin, S.B.Furber, "Scan testing of micropipelines", Proc. 13th IEEE VLSI Test Symposium, Princeton, New Jersey, USA, May 1-3, 1995, pp. 296-301.
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There are several different ways to implement an asynchronous adder, and each has particular testability characteristics. In this paper the stuck-at fault model is used to describe fault effects in the various adder implementations. We show that stuck-at faults on the data dependent control lines of the single-rail adder can cause both premature and delayed firings of its control outputs. The choice of single-rail, dual-rail or combined single and dual-rail (hybrid) data encoding techniques brings different trade-offs between the testability, performance and area overhead. A case study of an asynchronous comparator demonstrates that a hybrid implementation brings a reasonable compromise between the area overhead, performance degradation and testing costs.
O. A. Petlin, C. Farnsworth, S. B. Furber, "Design for testability of an asynchronous adder", Proc. of IEE Colloquium on Design and Test of Asynchronous Systems, London, UK, 28 Feb., 1996, pp. 5/1- 5/9.
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The design of an asynchronous block sorter and issues relating to its testability are discussed in this paper. The sorter takes an input data stream and sends it to the output sorted in descending order. The testable structure of the block sorter is implemented using the built-in self test (BIST) design methodology. A novel technique for changing the operation mode of the sorting cells of the block sorter which allows them to be set to normal operation mode or BIST mode sequentially or in parallel respectively is described. In BIST mode the sorting cells are tested in parallel reducing the overall test application time of the sorter. Fault simulation results reveal 100% testability of both single stuck-at-output faults at the high-level representation of the block sorter and all stuck-at faults inside data processing blocks of its sorting cells. The total area overhead of the BIST block sorter is 15.7%.
O.A.Petlin, C.Farnsworth, S.B.Furber, "The built-in self test design of an asynchronous block sorter", submitted to Euro-DAC'96, Geneva, Switzerland, Sept. 1996.
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The micropipeline approach offers a good engineering framework to design complex asynchronous VLSI circuits. An asynchronous ARM6 microprocessor (AMULET1), implemented using a two-phase signalling protocol, has proved the practical feasibility of the micropipeline design approach. A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register is presented in this paper. All the stage registers of the micropipeline are implemented using the proposed asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode. The test procedure described in this paper provides for the detection of all single stuck-at faults in the micropipeline. It is shown that delay faults in the combinational logic blocks of the BIST micropipeline can be tested by using BILBO registers of a doubled size.
O.A.Petlin, S.B.Furber, "Built-in self-testing of micropipelines", submitted to ICCD'96, Taxes, USA, Oct. 7-9, 1996.
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A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential circuits provides for the separate testing of the combinational logic block and the memory elements. The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic block. A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach.
O.A.Petlin, S.B.Furber, A.M.Romankevich, V.V.Groll, "Designing asynchronous sequential circuits for random pattern testability", IEE Proc.-Comput. Digit. Tech., Vol. 142, No. 4, July 1995.
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A relationship between the power consumption and the testability of CMOS VLSI circuits is demonstrated in this paper. The method used to estimate this correlation is based on elements of information theory. It is shown that the average output information content of a circuit node is proportional to its signal transition probability. As a consequence, design for low power consumption and design for testability are in direct conflict. The resolution of this conflict lies in separating the testing issues from the low power issues by giving the circuit distinct operating and test modes.
O.A.Petlin, S.B.Furber, "Power consumption and testability of CMOS VLSI circuits", submitted to IEEE Transactions on CAD
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C-elements are used widely in asynchronous VLSI circuits. Fabrication faults in some C-elements can be undetectable by logic testing. Testable designs of static CMOS C-elements are given in this paper which provide for the detection of single line stuck-at and stuck-open faults. We show that driving the feedback transistors in the proposed testable static C-element transforms its sequential function into a combinational AND or OR function depending on the driving logic value. This simplifies the testing of asynchronous circuits which incorporate a large number of state holding elements. The scan testable C-element described can be used in scan testing of the asynchronous circuit making the states of its memory elements controllable and observable.
O.A.Petlin, S.B.Furber, "Detecting fabrication faults in C-elements", submitted to IEEE Journal on VLSI Systems
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C-elements are used widely in asynchronous VLSI circuits. Fabrication faults in some CMOS C-elements can be undetectable by logic testing. Testable designs of static symmetric and asymmetric C-elements are given in this report which provide for the detection of single line stuck-at and stuck-open faults. We show that driving feedback transistors in the proposed testable static C-elements transforms their sequential functions into combinational AND and OR functions or into repeaters of one of their inputs depending on the driving logic value. This simplifies the testing of asynchronous circuits which incorporate a large number of state holding elements. The scan testable C-element described can be used in scan testing of the asynchronous circuit making the states of its memory elements controllable and observable.
O.A.Petlin, S.B.Furber, "Designing C-elements for testability", Technical Report UMCS-95-10-2, Department of Computer Science, University of Manchester, UK, 1995.
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An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a two-phase signalling protocol, and the latest release of the AMULET2e embedded controller, implemented using four-phase signalling, have proved the practical feasibility of the micropipeline design approach. A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register is presented in this paper. All the stage registers of the micropipeline are implemented using the proposed asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode. The test procedure described in this paper provides for the detection of all single stuck-at faults in the micropipeline. It is shown that delay faults in the combinational logic blocks of the BIST micropipeline can be tested by using BILBO registers of a doubled size.
O.A.Petlin, S.B.Furber, "Built-In Self-Testing of Micropipelines", ASYNC'97, Netherlands, Mar., 1997.
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