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Asynchronous SoC Interconnect and GALS

With the construction of the AMULET3i system, the groups work moved outwards in the system to encompass peripherals and interconnect design in addition to the processor core. In the AMULET3i system the SoC interconnect was provided by a shared, bidirectional (tristate) asynchronous system bus called MARBLE. More recently we have moved from using bundled data to delay-insensitive signalling, and from shared buses to on-chip networks with the development of CHAIN.

MARBLE

MARBLE
MARBLE Bus

Our first-generation asynchronous SoC interconnect was a shared system bus, using separate multipoint channels for each of the address and (bidirectional) data paths. The single-rail, bundled data scheme was used throughout, with tristate lines for the datapath and centralised OR gates used to combine the individual device signalling wires to generate the bus request and acknowledge signals. Centralised address-decoding and (pipelined/hidden) arbitration were used. In this respect MARBLE was a direct asynchronous equivalent for the synchronous buses of the time. However, the key distinguishing features were firstly its clock-less operation, and secondly its use of split-transactions for EVERY transfer.

John Bainbridge's PhD describing the MARBLE Bus won the BCS Distinguished Disseration Award. John's PhD thesis is available online or in hardback published format (ISBN 1-85233-598-X) from Springer Verlag.

CHAIN

CHAIN

MARBLE used single-rail signalling and was therefore subject to the same timing validation problems as are synchronous buses. As a result our efforts moved towards delay-insensitivity and distributed on-chip networks to provide more flexible interconnect with guaranteed timing closure.

CHAIN is our self-timed Network-on-Chip (NoC) architecture. It uses fine-grained pipelining of narrow links with low-cost switch-nodes to allow a range of network topologies and peformances. CHAIN has been used in one of our smartcard chips.

Network Modelling

Network Modelling
Example CHAIN Bus

An MSc project completed by Will Lovett constructed a Java based modelling tool for investigation of different CHAIN network topologies. Will's MSc thesis is available online.

Quality of Service

QoS
One of the issues in any NoC is guaranteeing service qualities. This is particularly tricky in asynchronous systems where deadlock/blocking is a possibility. Tomaz Felicijan is currently looking at this for his PhD work.

Globally Asynchronous Locally Synchronous

GALS

We are looking at ways of deploying asynchronous interconnnect when combined with synchronous IP blocks, a methodology often referred to as Globally Asynchronous Locally Synchronous (GALS) design. Our work in this area (and some of the above) is part of a joint project with Cambridge University.

Publications List

  • Future Trends in SoC Interconnect
  • An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support.
  • An asynchronous low latency arbiter for Quality of Service (QoS) applications.
  • Quality of Service (QoS) for Asynchronous On-Chip Networks
  • Delay-Insensitive, Point-to-Point Interconnect using m-of-n Codes (ASYNC03)
  • CHAIN: A Delay Insensitive CHip Area INterconnect (IEEE Micro)
  • Chip Area Network Simulation (Will Lovett's MSc)
  • A Synthesisable Amulet Core for Smartcard Applications (ASYNC02)
  • Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding (ASYNC01)
  • Asynchronous System-on-Chip Interconnect (John Bainbridge's Ph.D)
  • MARBLE: An asynchronous On-Chip Macrocell Bus (Microprocessors & Microsystems)
  • AMULET3i -an Asynchronous System-on-chip (ASYNC00)
  • Asynchronous Macrocell Interconnect using MARBLE (ASYNC98)