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This project is currently running and plans to tape out low power functional units suited for use in third generation battery-powered DSP applications in about a year. At the top level of design, four-way parallelism will be used to achieve an overall performance of at least 160MOPS while keeping power dissipation at a minimum.
A Functional Unit comprises both arithmetic blocks and a Configuration Memory. The latter can be regarded as a control RAM and it is loaded prior to the execution of an algorithm. This allows the Functional Units to be optimally configured for a particular operation. The logic and circuit design of the multiplier and arithmetic blocks of a Functional Unit are central to lowering power since one or both are involved in practically every operation performed in the Unit. Current work is therefore investigating implementing these in low-power CMOS logic families such as SPL (Single-ended Pass-transistor Logic) and pass transistor logic. It is planned to use a mixture of circuit design styles for the functional units on the fabricated device.
Four-phase asynchronous timing is adopted to avoid the power overhead of generating and buffering a global clock, to enable switching between idle and full activity with negligible overhead, and to spread the circuit switching thus reducing EMI levels; all these are important features for the application areas considered.
The design is being targetted at a 0.18μm process using an in-house cell library together with application-specific cells for the arithmetic blocks. The fabricated chip will be evaluated for typical GSM operations. Here the challenge is to maximise the use of the available parallelism in order to optimise overall power requirements.
Publications about asynchronous DSP design work
- Exploiting typical DSP data access patterns and asynchrony for a low power multiported register bank
- An instruction buffer for a low-power DSP
- Reconfigurable latch controllers for low power asynchronous circuits
- A low-power asynchronous DSP for digital mobile phone chipsets
- Power reduction in self-timed circuits using early-open latch controllers
- CADRE: an asynchronous embedded DSP for mobile phone applications
- CADRE: a low-power, low-EMI DSP architecture for digital mobile phones
*The funding of this work by the EPSRC is gratefully acknowledged.