School of Computer Science Intranet

APT research areas

ARM System Architecture

By: S.B. Furber
Published by: Addison Wesley Longman (1996)
ISBN: 0-201-40352-8

The 2nd edition of this book is now available entitled
ARM System-on-Chip Architecture

The book describes the design and operation of the ARM processor, a 32-bit RISC microprocessor from ARM Ltd. Full details are given of the ARM and Thumb instructions sets and the memory management architecture. There is illustrated discussion of how the ARM instruction set supports high-level language constructs.

ARM products are described, including the ARM6, ARM7TDMI and ARM8 cores, the 600/610, 700/710, 810 and StrongARM and some information on the AMULET asynchronous ARM cores. Embedded system design using the ARM is covered, including the debug methodology, hardware system design principles and software issues. Examples include the ARM7500 NC chip, the GPS Butterfly and the VLSI Ruby II and VIP chips.

The book also includes brief details of the Apple Newton, the Acorn Archimedes and RiscPC and the ARM PIE card as illustrations of practical ARM applications.

The full Table of Contents is given below.

Aims

This book introduces the concepts and methodologies employed in designing microprocessors and in designing systems around microprocessors. The principles of microprocessor design are made concrete by extensive illustrations based upon the ARM.

The aim of the book is to assist the reader in understanding how microprocessors are designed and used, and why a modern processor is designed the way that it is. The reader who wishes to know only the general principles should find that the ARM illustrations add substance to issues which can otherwise appear somewhat ethereal; the reader who specifically wishes to understand design of the ARM should find that the general principles illuminate the rationale for the ARM being as it is.

Other commercial microprocessor architectures are not described in this book. The reader who wishes to make a comparative study of such architectures will find the required information on the ARM here but must look elsewhere for information on other designs.

Audience

The book is intended to be of use to two distinct groups of readers:

Professional hardware and software engineers who are tasked with designing a product which incorporates an ARM processor, or who are evaluating the ARM for a product, should find the book helpful in their duties. Although there is considerable overlap with ARM technical publications, this book provides a broader context with more background. It is not a substitute for the manufacturer's data, since some detail has had to be omitted, but it should be useful as an introductory overview and adjunct to that data.
Students of computer science, computer engineering and electrical engineering should find the material of value at several stages in their courses. Some chapters are closely based on course material previously used in undergraduate teaching; some other material is drawn from a postgraduate course.

Prerequisite knowledge

This book is not intended to be an introductory text on computer architecture or computer logic design. Readers are assumed to have a level of familiarity with these subjects equivalent to that of a second year undergraduate student in computer science or computer engineering. Some first year material is presented, but this is more by way of a refresher than as a first introduction to this material.

No prior familiarity with the ARM processor is assumed.

Preface v

1 An Introduction to Processor Design 1

1.1 Processor architecture and organization 2
1.2 Abstraction in hardware design 4
1.3 MU0 - a simple processor 8
1.4 Instruction set design 15
1.5 Processor design trade-offs 21
1.6 The Reduced Instruction Set Computer 26
1.7 Design for low power consumption 30
1.8 Examples and exercises 34

2 The ARM Architecture 37

2.1 The Acorn RISC Machine 38
2.2 Architectural inheritance 39
2.3 The ARM programmer's model 41
2.4 ARM development tools 46
2.5 Example and exercises 50

3 ARM Assembly Language Programming 51

3.1 Data processing instructions 52
3.2 Data transfer instructions 58
3.3 Control flow instructions 66
3.4 Writing simple assembly language programs 72
3.5 Examples and exercises 75

4 ARM Organization and Implementation 77

4.1 ARM organization 78
4.2 ARM instruction execution 82
4.3 ARM implementation 86
4.4 The ARM coprocessor interface 101
4.5 Design tools 103
4.6 Examples and exercises 107

5 The ARM Instruction Set 109

5.1 Introduction 110
5.2 Exceptions 113
5.3 Conditional execution 117
5.4 Branch and Branch with Link (B, BL) 119
5.5 Branch and eXchange instructions (BX) 121
5.6 Software Interrupt (SWI) 122
5.7 Data processing instructions 124
5.8 Multiply instructions 128
5.9 Single word and unsigned byte data transfer instructions 130
5.10 Half-word and signed byte data transfer instructions 133
5.11 Multiple register transfer instructions 135
5.12 Swap memory and register instructions (SWP) 137
5.13 Status register to general register transfer instructions 138
5.14 General register to status register transfer instructions 139
5.15 Coprocessor instructions 141
5.16 Coprocessor data operations 142
5.17 Coprocessor data transfers 143
5.18 Coprocessor register transfers 145
5.19 Unused instruction space 147
5.20 Memory faults 149
5.21 ARM architecture variants 153
5.22 Example and exercises 157

6 Architectural Support for High-Level Languages 159

6.1 Abstraction in software design 160
6.2 Data types 161
6.3 Floating-point data types 167
6.4 The ARM floating-point architecture 172
6.5 Expressions 178
6.6 Conditional statements 180
6.7 Loops 183
6.8 Functions and procedures 185
6.9 Use of memory 191
6.10 Run-time environment 196
6.11 Examples and exercises 197

7 The Thumb Instruction Set 199

7.1 The Thumb bit in the CPSR 200
7.2 The Thumb programmer's model 201
7.3 Thumb branch instructions 203
7.4 Thumb software interrupt instruction 205
7.5 Thumb data processing instructions 206
7.6 Thumb single register data transfer instructions 209
7.7 Thumb multiple register data transfer instructions 211
7.8 Thumb implementation 213
7.9 Thumb applications 215
7.10 Example and exercises 216

8 Architectural Support for System Development 219

8.1 The ARMulator 220
8.2 The JTAG boundary scan test architecture 221
8.3 The ARM debug architecture 228
8.4 The Partner-ET ROM-ICE 233
8.5 The Advanced Microcontroller Bus Architecture (AMBA) 234
8.6 The ARM reference microcontroller 239
8.7 Example and exercises 241

9 ARM Processor Cores 243

9.1 ARM6 244
9.2 ARM7TDMI 249
9.3 ARM8 254
9.4 AMULET1&2 259
9.5 Examples and exercises 269

10 Memory Hierarchy 271

10.1 Memory size and speed 272
10.2 Caches 273
10.3 Memory management 281
10.4 Examples and exercises 286

11 Architectural Support for Operating Systems 287

11.1 An introduction to operating systems 288
11.2 The ARM system control coprocessor 291
11.3 ARM MMU architecture 294
11.4 Synchronization 301
11.5 Context switching 302
11.6 Input/Output 304
11.7 Example and exercises 308

12 ARM Processor Chips 309

12.1 The ARM600 and ARM610 310
12.2 The ARM700 and ARM710 321
12.3 The ARM810 326
12.4 The StrongARM 329
12.5 Example and exercises 338

13 ARM Systems 339

13.1 The ARM memory interface 340
13.2 The Platform Independent Evaluation card 350
13.3 The Acorn Archimedes 355
13.4 The Acorn Risc PC 357
13.5 The Apple Newton 362
13.6 Examples and exercises 366

14 Embedded ARM Processor Cores 369

14.1 GEC Plessey Semiconductors Butterfly microcontroller 370
14.2 The VLSI Ruby II Advanced Communication Processor 373
14.3 The VLSI ISDN Subscriber Processor 375
14.4 The ARM7500 378
14.5 AMULET2e 382
14.6 Examples and exercises 386

Appendix: Computer Logic 389

Glossary 397

Bibliography 405

Index 409

Figures

Figures and tables are available as gzipped PostScript files by FTP, each file containing all the figures and tables (but not photos) from a chapter arranged as one figure or table per page, each page being a titled landscape slide. The PostScript was generated from Microsoft PowerPoint v4 running on an Apple Mac and has been tested for 'ghostview' compatibility.

The figures and tables are made freely available on the understanding that any course which makes use of them will have this book as a recommended text.

Get them from here.

Please email S.B. Furber if you use these figures as I am interested in tracking their use.

Errata

The following changes were made for the 2nd and subsequent print runs of the book:

page 4, 1st para, line 5:

'...switching actions is used...' should read '...switching actions are used...'.

page 57, MUL and MLA instruction examples:

'...[32:0]' should be '...[31:0]' in both cases.

page 64, Figure 3.2:

the addresses on all four illustrations should increase by multiples of words, not bytes.
Hence '1003' should be '100c' and '1006' should be '1018'.
Note: the postscript figures available by FTP have been updated to reflect this change.

page 68, 1st code example, 2nd line:

the comment is wrong; '...; r1 := r0 - r2' should be '...; r1 := r1 + r0 - r2'

page 168, Equation 12:

'...1.1111001 x...' should be '...1.1111001011 x...'

page 203, Figure 7.2:

BL and BX both include 'H' bit; it is not made clear that this has a different meaning in each case. The third paragraph on page 204 should be extended to read:
'The fourth format maps directly onto the ARM BX instruction (see Section 5.5 on page 121); here 'H' can be set to select a 'Hi' register (r8 to r15).

page 256, last para, 1st line:

'...is show in...' should read '...is shown in...'.

page 385, Table 14.2:

we can now add additional data; the Power figure is 140 mW and the MIPS/W figure is 285.

page 409, AMBA index entry:

The main AMBA reference is on page 234, so change entry to 'AMBA 234, 370'.

The following errors occur in all print runs:

page 69:

The three examples of STM and LDM instructions on this page should all have base register write-back enabled: LDMFA r13!,...
In the 2nd edition of the book these examples also use LDMFD, STMFD in line with the ARM Procedure Call Standard stack model instead of LDMFA, STMFA.

page 162, under 'Number ranges':

'0 to 4 294 976 295...' should read
'0 to 4 294 967 295...'.

page 163, under 'Signed integers':

'-2 147 488 148 to +2 147 488 147...' should read
'-2 147 483 648 to +2 147 483 647...'.

APT Group