Speeding Up Verilog Gate-Level Simulation with Bi-Partitioning

Lilian Janin, Doug Edwards

Abstract

Iterative design methodologies based on a simulation-debugging-update cycle form the basis of Verilog design development. An automated flow to speed up iterative design cycles is presented here. Compilation speedup is obtained by partitioning the circuit in order to exploit the locality of code updates during a typical iteration, in order to recompile only the modified parts of the design. Simulation speedup is obtained by interfacing multiple instances of the same simulator together through a cosimulation interface, either on single-core or dual-core computers. Particular care is taken in the design of the cosimulation interface to ensure the same accuracy as during a single- kernel simulation. A smartcard circuit embedding an asynchronous ARM processor is used as a demonstrator. The speedup is analysed on both single and dual core machines with gate-level simulation. An unexpected result is that even on a single-core computer, in some circumstances, partitioning a simulation and simulating both parts simultaneously leads to some speedup in spite of the losses due to the cosimulation interface. During the iterative design cycle experiments, the main result is a 30% speedup achieved with all the simulators on a single core and 50% speedup on dual-cores.

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