The Advanced Processor Technologies Research Group

APT Group Publications

by Author

These are in reverse chronological order.
(Lists may not be comprehensive: these are the ones passed to/discovered by the webmaster.)

In some cases only more recent publications are shown on this page, in which cases a full list is linked at the bottom.

Steve Furber

• Synapse-Centric Mapping of Cortical Models to the SpiNNaker Neuromorphic Architecture
• Bio-inspired massively-parallel computation
• The SpiNNaker project
• Large-Scale Neuromorphic Computing Systems
• Neuromorphic sampling on the SpiNNaker and Parallella chip multiprocessors
• Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multi-Symbol Chip Links. Application to SpiNNaker 2-of-7 Links
• Efficient SpiNNaker simulation of a heteroassociative memory using the Neural Engineering Framework
• Large-scale simulations of plastic neural networks on neuromorphic hardware
• Brain-inspired computing
• Network traffic exploration on a many-core computing platform: SpiNNaker real-time traffic visualiser
• Transport-Independent Protocols for Universal AER Communications
• An efficient SpiNNaker implementation of the Neural Engineering Framework
• Accuracy and Efficiency in Fixed-Point Neural ODE Solvers
• Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms
• Live demonstration: Real-time event-driven object recognition on SpiNNaker
• ConvNets Experiments on SpiNNaker
• Breaking The Millisecond Barrier On SpiNNaker: Implementing Asynchronous Event-Based Plastic Models With Microsecond Resolution
• Scalable Energy-Efficient, Low-Latency Implementations of Spiking Deep Belief Networks on SpiNNaker
• Reliable computation with unreliable computers
• Live Demonstration: Handwritten Digit Recognition Using Spiking Deep Belief Networks on SpiNNaker
• Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM
• A framework for plasticity implementation on the SpiNNaker neural architecture
• Markov Chain Monte Carlo inference on graphical models using event-based processing on the SpiNNaker neuromorphic architecture
• SpiNNaker: Enhanced multicast routing
• Towards Real-World Neurorobotics: Integrated Neuromorphic Visual Attention
• SpinNNaker: The world's biggest NoC
• A framework for plasticity implementation on the SpiNNaker neural architecture
• Optimising the Overall Power Usage on the SpiNNaker Neuromimetic Platform
• Real-Time Million-Synapse Simulation of Rat Barrel Cortex
• SpiNNaker - programming model
• Engineering a thalamo-cortico-thalamic circuit on SpiNNaker: a preliminary study towards modelling sleep and wakefulness
• Event-based neural computing on an autonomous mobile platform
• The SpiNNaker Project
• On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
• A real-time simulator of a biological visual system composed of a silicon retina and SpiNNaker chips
** FULL LIST **

Jim Garside

• HAPPY: Hybrid Address-based Page Policy in DRAMs
  
• DReAM: Dynamic Re-arrangement of Address Mapping to Improve
• Asynchronous Dataflow De-Elastisation For Efficient Heterogeneous Synthesis
• On-chip Order-Exploiting Routing Table Minimization for a Multicast Supercomputer Network
• AutoCLK: A Promising Approach Toward GALSification
• Optimizing Indirect Branches in Dynamic Binary Translators
• Network traffic explorationon a many-core computing platform: SpiNNaker real-time traffic visualiser
• Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
• Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
• Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults
• De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits
• Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
• Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain
• High-level Synthesis of GALS Systems
• SpiNNaker - programming model
• Protecting QDI Interconnects from Transient Faults Using Delay-Insensitive Redundant Check Codes
• On-Line Detection of the Deadlocks Caused by Permanently Faulty Links in Quasi-Delay Insensitive Networks on Chip
• An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults
• Automatic data path extraction in large-scale register-transfer level designs
** FULL LIST **

David R.Lester

• Transport-Independent Protocols for Universal AER Communications
• Overview of the SpiNNaker system architecture
• SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
• A location-independent direct link neuromorphic interface
• SpiNNaker: A 1W 18-core System-on-Chip for Massively-Parallel Neural Network Simulation
• Overview of the SpiNNaker system architecture
• The World's Shortest Correct Exact Real Arithmetic Program?
• Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
• Spiking Neural PID Controllers
• A monadic approach to automated reasoning for Bluespec SystemVerilog Innovations in Systems and Software Engineering
• Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture
• A communication infrastructure for a million processor machine
• High Accuracy Machine-Efficient Chebyshev Approximations: an Application to Spectral Methods for Sobolev Spaces
• SpiNNaker: The design automation problem
• SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
• Computable Function Representation Using Effective Chebyshev Polynomial
• Stochastic Formal Methods: An Application to Accuracy of Numeric Software
• FUNCTIONAL PEARL: Enumerating the rationals
• Using PVS to validate the Algorithms of an Exact Arithmetic
• A Constructive Algorithms for finding the Exact Roots of Polynomials with Computable Real Coefficients
• A Survey of Exact Arithmetic Implementations
• Effective Continued Fractions
• Exact Arithmetic and the Korteweg-de Vries Equation
• The Correctness of an Implementation of Exact Arithmetic
• Validating the Correctness of an Exact Arithmetic Package
• Towards a machine-checked congruence for exact arithmetic

Mikel Luján

• HAPPY: Hybrid Address-based Page Policy in DRAMs
  
• DReAM: Dynamic Re-arrangement of Address Mapping to Improve
• Optimizing Indirect Branches in Dynamic Binary Translators
• A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip
• Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
• AMON: Advanced Mesh-like Optical NoC
• Effective Barrier Synchronization on Intel Xeon Phi Coprocessor
• Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM
• Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
• SpiNNaker: Enhanced multicast routing
• An Empirical Evaluation of High-level Synthesis Languages and Tools for Database Acceleration
• On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
• SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
• Optimizing software runtime systems for speculative parallelization
** FULL LIST **

Luis Plana

• Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multi-Symbol Chip Links. Application to SpiNNaker 2-of-7 Links
• Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
• ConvNets Experiments on SpiNNaker
• Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
• Breaking The Millisecond Barrier On SpiNNaker: Implementing Asynchronous Event-Based Plastic Models With Microsecond Resolution
• A framework for plasticity implementation on the SpiNNaker neural architecture
• SpiNNaker: Enhanced multicast routing
• A framework for plasticity implementation on the SpiNNaker neural architecture
• SpiNNaker - programming model
• Event-based neural computing on an autonomous mobile platform
• The SpiNNaker Project
• On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
• A real-time simulator of a biological visual system composed of a silicon retina and SpiNNaker chips
** FULL LIST **

Steve Temple

• Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multi-Symbol Chip Links. Application to SpiNNaker 2-of-7 Links
• SpiNNaker: Enhanced multicast routing
• SpiNNaker - programming model
• The SpiNNaker Project
• On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
• Overview of the SpiNNaker system architecture
• SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
• A location-independent direct link neuromorphic interface
• SpiNNaker: A 1W 18-core System-on-Chip for Massively-Parallel Neural Network Simulation
** FULL LIST **

Alexander Rast

• Transport-Independent Protocols for Universal AER Communications
• Towards Real-World Neurorobotics: Integrated Neuromorphic Visual Attention
• SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
• A location-independent direct link neuromorphic interface
• Live demonstration: Ethernet communication linking two large-scale neuromorphic systems
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• A forecast-based STDP rule suitable for neuromorphic implementation
• Power-efficient simulation of detailed cortical microcircuits on SpiNNaker
• Visualising Large-Scale Neural Network Models in Real-Time
• Event-Driven MLP Implementation on Neuromimetic Hardware
• A hierarchical configuration system for a massively parallel neural hardware platform
• Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
• An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
• A forecast-based biologically-plausible STDP learning rule
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Maintaining real-time synchrony on SpiNNaker
• A General-Purpose Model Translation System for a Universal Neural Chip
• Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture
• Algorithm and Software for Simulation of Spiking Neural Networks on the Multi-Chip SpiNNaker System
• Implementing Spike-Timing-Dependent Plasticity on SpiNNaker Neuromorphic Hardware
• The Leaky Integrate-and-Fire Neuron: A Platform for Synaptic Model Exploration on the SpiNNaker Chip
• Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
• Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
• Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
• Optimal Connectivity In Hardware-Targetted MLP Networks
• A Universal Abstract-Time Platform for Real-Time Neural Networks

Alasdair Rawsthorne

• Consistent Windowing Interfaces in Distributed Heterogeneous Environments.
• Exploiting Hardware Resources: Register Assignment across Method Boundaries

John V Woods

• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• The Amulet chips: Architectural Development for Asynchronous Microprocessors
• Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
• System Level Modelling for SpiNNaker CMP System
• Efficient Modelling of Spiking Neural Networks on a Scalable Chip Multiprocessor
• AMULET3i - an Asynchronous System-on-Chip
• AMULET1: An Asynchronous ARM Microprocessor
• Occam: An Asynchronous Hardware Description Language?
• Simulating Asynchronous Architectures on Transputer Networks.
• Timing Verification for Asynchronous Design.
• Investigations into Micropipeline Latch Design Styles.
• Dealing with Time Modelling Problems in Parallel Models of Asynchronous Computer Architectures.
• Analysing the Timing Error in Distributed Simulations of Asynchronous Computer Architectures.
• AMULET1: A Micropipelined ARM
• Building Parallel Distributed Models for Asynchronous Computer Architectures
• Distributed Simulation of Asynchronous Computer Architectures: The Program Driven Conservative Approach
• The Design and Evaluation of an Asynchronous Microprocessor
• A Micropipelined ARM
• Register Locking in an Asynchronous Microprocessor

Nick Filer

• DECOR: Distributed construction of load balanced routing trees for many to one sensor networks
• The rise and fall of spatio-temporal clusters in mobile ad hoc networks
• Distributed expectation-based spatio-temporal cluster detection for pocket switched networks

Vasilis Pavlidis

• Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs
• Interconnect Design Tradeoffs for Silicon and Glass Interposers
• Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise
• Effect of Process Variations in 3D Global Clock Distribution Networks
• Enhanced Wafer Matching Heuristics for 3-D ICs
• Inter-Plane Communication Methods for 3-D ICs
• A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
• Voltage Propagation Method for 3-D Power Grid Analysis
• The Combined Effect of Process Variations and Power Supply Noise

Dirk Koch

• Portable module relocation and bitstream compression for Xilinx FPGAs
• Hierarchical reconfiguration of FPGAs

Antoniu Pop

• Effective Barrier Synchronization on Intel Xeon Phi Coprocessor
• Compiler/Runtime Framework for Dynamic Dataflow Parallelization of Tiled Programs
• Aftermath: A graphical tool for performance analysis and debugging of fine-grained task-parallel programs and run-time systems
• TERAFLUX: Harnessing dataflow in next generation teradevices
• Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages
• Energy-aware parallelization flow and toolset for C code
• Correct and Efficient Bounded FIFO Queues

Javier Navaridas

• A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip
• An Efficient Shortest-Path Routing Algorithm in the Data Centre Network DPillar
• On Routing Algorithms for the DPillar Data Centre Networks
• Routing Algorithms for Recursively-Defined Data Centre Networks
• Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
• AMON: Advanced Mesh-like Optical NoC
• Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
• Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults
• SpiNNaker: Enhanced multicast routing
• An Empirical Evaluation of High-level Synthesis Languages and Tools for Database Acceleration
• Protecting QDI Interconnects from Transient Faults Using Delay-Insensitive Redundant Check Codes
• On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
• An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults
• SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
• Transient fault tolerant QDI interconnects using redundant check code
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
• Population-Based Routing in the SpiNNaker Neuromorphic Architecture
• Reservation-based Network-on-Chip timing models for large-scale architectural simulation
• Scalable Communications for a Million-Core Neural Processing Architecture
• Indirect cube: A power-efficient topology for compute clusters
• Simulating and evaluating interconnection networks with INSEE
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• Twisted Torus Topologies for Enhanced Interconnection Networks
• Reducing complexity in tree-like computer interconnection networks
• SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
• Understanding the Interconnection Network of SpiNNaker
• Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric

Eva Navarro-Lopez

• Neuro-DYVERSE: building hybrid systems neuroscience

Simon Davidson

• A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection
• Large-Scale On-Chip Dynamic Programming Network Inferences using Moderated Inter-Core Communication
• SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
• SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip

Michael Hopkins

• Accuracy and Efficiency in Fixed-Point Neural ODE Solvers

Alan Stokes

• Transport-Independent Protocols for Universal AER Communications

Will Toms

• Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
• Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain
• Self-Timed Section Carry Based Carry Lookahead Adders and the Concept of Alias Logic
• Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
• Indicating combinational logic decomposition
• A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
• M-of-N Code Decomposition for Indicating Combinational Logic
• Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks
• Return Value Prediction meets Information Theory
• Efficient Synthesis of Speed Independent Combinational Logic Circuits
• Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes

John Mawer

• Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM
• An Empirical Evaluation of High-level Synthesis Languages and Tools for Database Acceleration

Andy Nisbet

• Effective Barrier Synchronization on Intel Xeon Phi Coprocessor
• Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM

Christos Kotselidis

• Clustering JVMs with Software Transactional Memory Support
• Improving Performance by Reducing Aborts in Hardware Transactional Memory
• On the Performance of Contention Managers for Complex Transactional Memory Benchmarks
• Profiling Transactional Memory Applications
• Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
• DiSTM: A Software Transactional Memory Framework for Clusters
• Advanced Concurrency Control for Transactional Memory using Transaction Commit Rate
• Lee-TM: A Non-trivial Benchmark for Transactional Memory

Abbas Kiasari

• An Efficient Shortest-Path Routing Algorithm in the Data Centre Network DPillar
• On Routing Algorithms for the DPillar Data Centre Networks
• Routing Algorithms for Recursively-Defined Data Centre Networks

Linda Brackenbury

** LIST **

Doug Edwards

** LIST **

Chris Kirkham

** LIST **

Ian Watson

** LIST **