The Advanced Processor Technologies Research Group

Jim Garside: publications

1. HAPPY: Hybrid Address-based Page Policy in DRAMs
   
2. DReAM: Dynamic Re-arrangement of Address Mapping to Improve
3. Asynchronous Dataflow De-Elastisation For Efficient Heterogeneous Synthesis
4. On-chip Order-Exploiting Routing Table Minimization for a Multicast Supercomputer Network
5. AutoCLK: A Promising Approach Toward GALSification
6. Optimizing Indirect Branches in Dynamic Binary Translators
7. Network traffic explorationon a many-core computing platform: SpiNNaker real-time traffic visualiser
8. Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
9. Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
10. Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults
11. De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits
12. Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
13. Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain
14. High-level Synthesis of GALS Systems
15. SpiNNaker - programming model
16. Protecting QDI Interconnects from Transient Faults Using Delay-Insensitive Redundant Check Codes
17. On-Line Detection of the Deadlocks Caused by Permanently Faulty Links in Quasi-Delay Insensitive Networks on Chip
18. An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults
19. Automatic data path extraction in large-scale register-transfer level designs
20. Overview of the SpiNNaker system architecture
21. SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
22. Automatic controller detection for large scale RTL designs
23. Transient fault tolerant QDI interconnects using redundant check code
24. SpiNNaker: A 1W 18-core System-on-Chip for Massively-Parallel Neural Network Simulation
25. SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
26. Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches
27. Overview of the SpiNNaker system architecture
28. An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery
29. Scalable Communications for a Million-Core Neural Processing Architecture
30. The Amulet chips: Architectural Development for Asynchronous Microprocessors
31. Fault-Tolerant Delay-Insensitive Inter-Chip Communication
32. A Programmable Adaptive Router for a GALS Parallel System
33. Design and implementation of an energy efficient, parallel, asynchronous DSP
34. Sensitive Registers: a Technique for Reducing the Fetch Bandwidth in Low-Power Microprocessors
35. Modernisation of Teaching in Embedded Systems Design - An International Collaborative Project
36. A Low-Power Processor Architecture Optimized for Wireless Devices.
37. A Quasi-Delay-Insensitive Method to Overcome Transistor Variation.
38. Energy efficient functional unit for a parallel asynchronous DSP.
39. An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
40. A CAM with mixed serial-parallel comparison for use in low energy caches
41. Designing Robust Asynchronous Circuits
42. An asynchronous copy-back cache architecture
43. Early Output Logic using Anti-Tokens
    
44. SPA - A Secure Amulet Core for Smartcard Applications
45. Adaptive Pipeline Structures for Speculation Control
46. Adaptive Pipeline Depth Control for Processor Power-Management
47. An Asynchronous Victim Cache
48. An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks
49. SPA - A Synthesisable Amulet Core for Smartcard Applications
50. A Comparative Power Analysis of an Asynchronous Processor
51. Power Management in the AMULET Microprocessors
52. AMULET3i Cache Architecture
53. A Practical Comparison of Asynchronous Design Styles
54. AMULET3: a 100 MIPS Asynchronous Embedded Processor
55. AMULET3i - an Asynchronous System-on-Chip
56. AMULET3i - an Asynchronous System-on-Chip
57. AMULET3 Revealed
58. Memory Faults in Asynchronous Microprocessors
59. Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
60. AMULET2e: An Asynchronous Embedded Controller
61. Asynchronous Embedded Control
62. Re-configurable Latch Controllers for Low Power Asynchronous Circuits
63. AMULET3: A High-Performance Self-Timed ARM Microprocessor
64. AMULET1: An Asynchronous ARM Microprocessor
65. A Result Forwarding Mechanism for Asynchronous Pipelined Systems
66. AMULET2e: An Asynchronous Embedded Controller
67. The AMULET2e Cache System.
68. AMULET2e.
69. AMULET2e.
70. A Comparison of Power Consumption in some CMOS Adder Circuits
71. A Cache Line Fill Circuit for a Micropipelined Asynchronous Microprocessor
72. AMULET1: A Micropipelined ARM
73. The Design and Evaluation of an Asynchronous Microprocessor
74. A CMOS VLSI Implementation of an Asynchronous ALU
75. A Micropipelined ARM
76. Register Locking in an Asynchronous Microprocessor