The Advanced Processor Technologies Research Group

Steve Furber: publications

1. Synapse-Centric Mapping of Cortical Models to the SpiNNaker Neuromorphic Architecture
2. Bio-inspired massively-parallel computation
3. The SpiNNaker project
4. Large-Scale Neuromorphic Computing Systems
5. Neuromorphic sampling on the SpiNNaker and Parallella chip multiprocessors
6. Efficient SpiNNaker simulation of a heteroassociative memory using the Neural Engineering Framework
7. Large-scale simulations of plastic neural networks on neuromorphic hardware
8. Brain-inspired computing
9. Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multi-Symbol Chip Links. Application to SpiNNaker 2-of-7 Links
10. Network traffic exploration on a many-core computing platform: SpiNNaker real-time traffic visualiser
11. Transport-Independent Protocols for Universal AER Communications
12. An efficient SpiNNaker implementation of the Neural Engineering Framework
13. Accuracy and Efficiency in Fixed-Point Neural ODE Solvers
14. Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms
15. Real-time event-driven spiking neural network object recognition on the SpiNNaker platform
16. Live demonstration: Real-time event-driven object recognition on SpiNNaker
17. ConvNets Experiments on SpiNNaker
18. Breaking The Millisecond Barrier On SpiNNaker: Implementing Asynchronous Event-Based Plastic Models With Microsecond Resolution
19. Scalable Energy-Efficient, Low-Latency Implementations of Spiking Deep Belief Networks on SpiNNaker
20. Reliable computation with unreliable computers
21. Live Demonstration: Handwritten Digit Recognition Using Spiking Deep Belief Networks on SpiNNaker
22. Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM
23. A framework for plasticity implementation on the SpiNNaker neural architecture
24. SpiNNaker: Enhanced multicast routing
25. Towards Real-World Neurorobotics: Integrated Neuromorphic Visual Attention
26. SpinNNaker: The world's biggest NoC
27. A framework for plasticity implementation on the SpiNNaker neural architecture
28. Optimising the Overall Power Usage on the SpiNNaker Neuromimetic Platform
29. Real-Time Million-Synapse Simulation of Rat Barrel Cortex
30. SpiNNaker - programming model
31. Engineering a thalamo-cortico-thalamic circuit on SpiNNaker: a preliminary study towards modelling sleep and wakefulness
32. Event-based neural computing on an autonomous mobile platform
33. The SpiNNaker Project
34. On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
35. A real-time simulator of a biological visual system composed of a silicon retina and SpiNNaker chips
36. Overview of the SpiNNaker system architecture
37. SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
38. Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System
39. Modeling Populations of Spiking Neurons for Fine Timing Sound Localization
40. A location-independent direct link neuromorphic interface
41. Spike-based learning of transfer functions with the SpiNNaker neuromimetic simulator
42. Power analysis of large-scale, real-time neural networks on SpiNNaker
43. Correctness and Performance of the SpiNNaker Architecture
44. Live demonstration: Ethernet communication linking two large-scale neuromorphic systems
45. SpiNNaker: A 1W 18-core System-on-Chip for Massively-Parallel Neural Network Simulation
46. TO BUILD A BRAIN-Getting to the bottom of how our brains work is a monumental task, but some innovative computational tricks and a million ARM processors could help
47. Live Demo: Spiking ratSLAM: Rat hippocampus cells in spiking neural hardware
48. A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection
49. Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
50. Creating, documenting and sharing network models
51. Modelling normal and impaired letter recognition: Implications for understanding pure alexic reading
52. Large-Scale On-Chip Dynamic Programming Network Inferences using Moderated Inter-Core Communication
53. A forecast-based STDP rule suitable for neuromorphic implementation
54. Power-efficient simulation of detailed cortical microcircuits on SpiNNaker
55. Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
56. Managing a Massively-Parallel Resource-Constrained Computing Architecture
57. Population-Based Routing in the SpiNNaker Neuromorphic Architecture
58. Visualising Large-Scale Neural Network Models in Real-Time
59. Real Time On-Chip Implementation of Dynamical Systems with Spiking Neurons
60. Event-Driven MLP Implementation on Neuromimetic Hardware
61. SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
62. Overview of the SpiNNaker system architectur
63. The Impact of Technology Scaling in the SpiNNaker Chip Multiprocessor
64. An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
65. A hierarchical configuration system for a massively parallel neural hardware platform.
66. "Serial" Effects in Parallel Models of Reading
67. A forecast-based STDP rule suitable for neuromorphic implementation
68. Scalable Communications for a Million-Core Neural Processing Architecture
69. SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip
70. Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis
71. Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
72. Event-Driven SpiNNaker Simulation
73. A Novel Programmable parallel CRC Circuit
74. An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
75. A forecast-based biologically-plausible STDP learning rule
76. Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
77. Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
78. Distributed Configuration of Massively-Parallel Simulation on SpiNNaker Neuromorphic Hardware
79. Representing and Decoding Rank Order Codes Using Polychronization in a Network of Spiking Neurons
80. Maintaining real-time synchrony on SpiNNaker
81. A General-Purpose Model Translation System for a Universal Neural Chip
82. Interfacing Real-Time Spiking I/O with the SpiNNaker neuromimetic architecture
83. STDP pattern onset learning depends on background activity
84. Modeling Spiking Neural Networks on SpiNNaker
85. A Novel Programmable parallel CRC Circuit
86. Biologically Inspired Means for Rank-Order Encoding Images: A Quantitative Analysis
87. Algorithm and Software for Simulation of Spiking Neural Networks on the Multi-Chip SpiNNaker System
88. Implementing Spike-Timing-Dependent Plasticity on SpiNNaker Neuromorphic Hardware
89. The Leaky Integrate-and-Fire Neuron: A Platform for Synaptic Model Exploration on the SpiNNaker Chip
90. Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
91. SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
92. Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
93. Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
94. A communication infrastructure for a million processor machine
95. The Amulet chips: Architectural Development for Asynchronous Microprocessors
96. Adaptive Admission Control on the SpiNNaker MPSOC
97. Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors
98. A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture
99. Understanding the Interconnection Network of SpiNNaker
100. A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
101. Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
102. Optimal Connectivity In Hardware-Targetted MLP Networks
103. Evaluating Rank-order Code Performance Using A Biologically Derived Retinal Model
104. A Universal Abstract-Time Platform for Real-Time Neural Networks
105. Fault-Tolerant Delay-Insensitive Inter-Chip Communication
106. A Programmable Adaptive Router for a GALS Parallel System
107. System Level Modelling for SpiNNaker CMP System
108. SpiNNaker: The design automation problem
     
109. The Deferred Event Model for Hardware-Oriented Spiking Neural Networks
     
110. An Admission Control System for QoS Provision on a Best-effort GALS Interconnect
     
111. Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip
     
112. SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
     
113. Efficient Modelling of Spiking Neural Networks on a Scalable Chip Multiprocessor
     
114. An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
     
115. The Future of Computer Technology and its Implications for the Computer Industry
     
116. A GALS Infrastructure for a Massively Parallel Multiprocessor
     
117. Neural systems engineering
     
118. Maximising Information Recovery from Rank-Order Codes
     
119. Sparse Distributed Memory using Rank-Order Neural Codes
     
120. The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.
     
121. Information Recovery from Rank-Order Encoded Images
     
122. On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems.
     
123. High-Performance Computing for Systems of Spiking Neurons.
     
124. Future Trends in SoC Interconnect.
     
125. The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.
     
126. A spiking neural sparse distributed memory implementation for learning and predicting temporal sequences.
     
127. An associative memory for the on-line recognition and prediction of temporal sequences.
     
128. A system for transmitting a coherent burst of activity through a network of spiking neurons.
     
129. A low power embedded dataflow coprocessor.
     
130. Future Trends in SoC Interconnect
     
131. An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support.
132. A Sparse Distributed Memory based upon N-of-M Codes.
133. The Design of a Low-Power Asynchronous Multiplier.
134. Minimizing the Power Consumption of an Asynchronous Multiplier.
135. Design and Analysis of a Self-Timed Duplex Communication System.
136. The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip
137. An Asynchronous Ternary Logic Signalling System
138. An asynchronous low latency arbiter for Quality of Service (QoS) applications.
139. Designing Robust Asynchronous Circuits
140. An asynchronous copy-back cache architecture
141. Quality of Service (QoS) for Asynchronous On-Chip Networks
142. Prototyping a Digital Neural Network System-on-Chip using an Altera Excalibur Device
143. A Low-Power Asynchronous Multiplier
144. An Investigation into the Security of Self-timed Circuits
145. Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes
146. CHAIN: A Delay Insensitive CHip Area INterconnect
147. An Asynchronous Victim Cache
148. Validating the AMULET Microprocessors
149. Applying asynchronous techniques to a Viterbi decoder design
150. Power Management in the AMULET Microprocessors
151. Delay Insensitive System-on-Chip Interconnect Uning 1-of-4 Data Encoding
152. A Low-Power Self-Timed Viterbi Decoder
153. A Novel Area-Efficient Binary Adder
154. AMULET3: a 100 MIPS Asynchronous Embedded Processor
155. A Power-Efficient Duplex Communication System
156. An Asynchronous Viterbi Decoder
157. MARBLE: An Asynchronous On-Chip Macrocell Bus
158. On-chip timing reference for self-timed microprocessor
159. Kicking out the Clock
160. AMULET3i - an Asynchronous System-on-Chip
161. The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs
162. AMULET3 Revealed
163. AMULET2e: An Asynchronous Embedded Controller
164. The Design of an Asynchronous VHDL Synthesizer
165. Asynchronous Macrocell Interconnect using MARBLE
166. Asynchronous Embedded Control
167. Modelling and Simulation of Asynchronous Systems using the LARD Hardware Description Language
168. AMULET3: A High-Performance Self-Timed ARM Microprocessor
169. Behavioural Modelling of Asynchronous Systems for Power and Performance Analysis
170. AMULET1: An Asynchronous ARM Microprocessor
171. Built-In Self-Test Design of Micropipelines
172. AMULET2e: An Asynchronous Embedded Controller
173. Britain needs Manufacturing
174. Asynchronous Logic.
175. Breaking Step - the Return of Asynchronous Logic.
176. Design for Testability of an Asynchronous Adder.
177. Dynamic Logic in Four-Phase Micropipelines.
178. Four-Phase Micropipeline Latch Control Circuits.
179. AMULET2e.
180. Scan testing of asynchronous sequential circuits.
181. Scan testing of micropipelines.
182. Designing Asynchronous Sequential Circuits for Random Pattern Testability.
183. Designing C-elements for Testability.
184. AMULET1: A Micropipelined ARM
185. Transforming Architectural Models Into High Performance Concurrent Implementations
186. The Design and Evaluation of an Asynchronous Microprocessor
187. Breaking Step - the Return of Asynchronous Logic.
188. AMULET1 - An Asynchronous ARM Processor.
189. Computing without Clocks.
190. A Micropipelined ARM
191. Register Locking in an Asynchronous Microprocessor