The Advanced Processor Technologies Research Group

Luis Plana: publications

1. Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multi-Symbol Chip Links. Application to SpiNNaker 2-of-7 Links
2. Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
3. ConvNets Experiments on SpiNNaker
4. Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
5. Breaking The Millisecond Barrier On SpiNNaker: Implementing Asynchronous Event-Based Plastic Models With Microsecond Resolution
6. A framework for plasticity implementation on the SpiNNaker neural architecture
7. SpiNNaker: Enhanced multicast routing
8. A framework for plasticity implementation on the SpiNNaker neural architecture
9. SpiNNaker - programming model
10. Event-based neural computing on an autonomous mobile platform
11. The SpiNNaker Project
12. On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
13. A real-time simulator of a biological visual system composed of a silicon retina and SpiNNaker chips
14. Overview of the SpiNNaker system architecture
15. SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
16. Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System
17. A location-independent direct link neuromorphic interface
18. Live demonstration: Ethernet communication linking two large-scale neuromorphic systems
19. SpiNNaker: A 1W 18-core System-on-Chip for Massively-Parallel Neural Network Simulation
20. Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
21. Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
22. Event-Driven MLP Implementation on Neuromimetic Hardware
23. SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
24. Overview of the SpiNNaker system architecture
25. An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
26. A hierarchical configuration system for a massively parallel neural hardware platform.
27. Scalable Communications for a Million-Core Neural Processing Architecture
28. SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip
29. Event-Driven SpiNNaker Simulation
30. An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
31. Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
32. Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
33. Description-level optimisation of synthesisable asynchronous circuits.
34. Asynchronous Data-Driven Circuit Synthesis
35. Modeling Spiking Neural Networks on SpiNNaker
36. Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
37. SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
38. Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
39. Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
40. A communication infrastructure for a million processor machine
41. System-on-Chip Design and Implementation
42. Adaptive Admission Control on the SpiNNaker MPSOC
43. A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
44. Understanding the Interconnection Network of SpiNNaker
45. Asynchronous Data-Driven Circuit Synthesis
46. A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
47. Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
48. A Universal Abstract-Time Platform for Real-Time Neural Networks
49. Fault-Tolerant Delay-Insensitive Inter-Chip Communication
50. System Level Modelling for SpiNNaker CMP System
51. SpiNNaker: The design automation problem
    
52. An Admission Control System for QoS Provision on a Best-effort GALS Interconnect
    
53. Automatic Compilation of Data-Driven Circuits
    
54. SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor
    
55. An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
    
56. Performance-driven syntax-directed synthesis of asynchronous processors.
57. A GALS Infrastructure for a Massively Parallel Multiprocessor.
58. Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
59. The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip
60. SPA - A Secure Amulet Core for Smartcard Applications
61. An Investigation into the Security of Self-timed Circuits
62. SPA - A Synthesisable Amulet Core for Smartcard Applications