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APT Advanced Processor Technologies Research Group

The Advanced Processor Technologies Research Group


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Linda Brackenbury: publications

  1. Early stopping turbo decoders: a high-throughput, low-energy bit-level approach and implementation
  2. System-on-Chip Design and Implementation
  3. Pre-processing of Convolutional Codes for Reducing Decoding Power Consumption
  4. No-Handshake Asynchronous Survivor memory Unit for a Viterbi Decoder
  5. Lowering power in an experimental RISC processor
  6. Design and implementation of an energy efficient, parallel, asynchronous DSP
  7. Energy efficient functional unit for a compute-intensive asynchronous DSP.
  8. Energy efficient functional unit for a parallel asynchronous DSP.
  9. An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
  10. Design of asynchronous function unit & software development tools for a low-power DSP.
  11. Functional Unit for Low-Power DSP Architecture
  12. CADRE: an Asynchronous Embedded DSP for Mobile Phone Applications
  13. Low power asynchronous DSP for digital mobile phones.
  14. Applying asynchronous techniques to a Viterbi decoder design
  15. Combining SOI Technology and Asynchronous Design Techniques for Power Reduction.
  16. A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power
  17. CADRE: A Low-Power, Low-EMI DSP Architecture for Digital Mobile Phones
  18. A Low-Power Self-Timed Viterbi Decoder
  19. Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank
  20. The Optical Encryption of Digital Data
  21. Exploiting Asynchronous Self-Timed Techniques on SOI Technology for Low Power
  22. An Asynchronous Viterbi Decoder
  23. A low-power asynchronous DSP architecture for digital mobile phone chipsets
  24. An Instruction Buffer for a Low-Power DSP
  25. Power reduction in self-timed circuits using early-open latch controllers
  26. Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
  27. Re-configurable Latch Controllers for Low Power Asynchronous Circuits
  28. Optical solution to the Lee algorithm by use of symbolic substitution
  29. Differential register bank design for self timed differential bipolar technology
  30. Design and modelling of a high performance differential bipolar self-timed microprocessor
  31. Transforming Architectural Models Into High Performance Concurrent Implementations
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