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The Advanced Processor Technologies Research Group

Mikel Luján: publications

1. HAPPY: Hybrid Address-based Page Policy in DRAMs
   
2. DReAM: Dynamic Re-arrangement of Address Mapping to Improve
3. Optimizing Indirect Branches in Dynamic Binary Translators
4. A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip
5. Analysis of FPGA and Software Approaches to Simulate Unconventional Computer Architectures
6. AMON: Advanced Mesh-like Optical NoC
7. Effective Barrier Synchronization on Intel Xeon Phi Coprocessor
8. Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM
9. Accelerating Interconnect Analysis using High-Level HDLs and FPGA SpiNNaker as a Case Study
10. SpiNNaker: Enhanced multicast routing
11. An Empirical Evaluation of High-level Synthesis Languages and Tools for Database Acceleration
12. On Generating Multicast Routes for SpiNNaker, a Massively-Parallel System for Neural Net Simulation
13. SpiNNaker: Fault Tolerance in a Power- and Area- Constrained Large-Scale Neuromimetic Architecture
14. Optimizing software runtime systems for speculative parallelization
15. Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
16. Software transactional memories for Scala
17. Reservation-based Network-on-Chip timing models for large-scale architectural simulation
18. Architectural Support for Exploiting Fine Grain Parallelism
19. A case for Exiting a Transaction in the Context of Hardware Transactional Memory
20. SnCTM: Reducing False Transaction Aborts by Adaptively Changing the Source of Conflict Detection
21. Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
22. The Economics of Garbage Collection
23. Scalable Object-Aware Hardware Transactional Memory
24. Clustering JVMs with Software Transactional Memory Support
25. Improving Performance by Reducing Aborts in Hardware Transactional Memory
26. Modeling Spiking Neural Networks on SpiNNaker
27. Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware
28. SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
29. Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
30. On the Performance of Contention Managers for Complex Transactional Memory Benchmarks
31. Understanding the Interconnection Network of SpiNNaker
32. Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
33. Profiling Transactional Memory Applications
34. Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
35. An Object-Aware Hardware Transactional Memory System
36. DiSTM: A Software Transactional Memory Framework for Clusters
37. Advanced Concurrency Control for Transactional Memory using Transaction Commit Rate
38. A first insight into object-aware hardware transactional memory
39. Lee-TM: A Non-trivial Benchmark for Transactional Memory
40. Introducing Aspects to the Implementation of a Java Fork/Join Framework
41. Adaptive Loop Tiling for a Multi-cluster CMP
42. Speculative Parallelization - Eliminating the Overhead of Failure
43. A Study of a Transactional Parallel Routing Algorithm
44. Towards Intelligent Analysis Techniques for Object Pretenuring

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