The Advanced Processor Technologies Research Group

Doug Edwards: publications

1. De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits
2. Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
3. Automatic data path extraction in large-scale register-transfer level designs
4. Statistical Analysis Model of Nano-CMOS Variability with Intra-die Correlation Due to Proximity
5. Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
6. Self-Timed Section Carry Based Carry Lookahead Adders and the Concept of Alias Logic
7. Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
8. Critical path analysis in data-driven asynchronous pipelines
9. Survey of asynchronous networks-on-chip. (In Chinese)
10. Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches
11. Routing of Asynchronous Clos Networks
12. Indicating combinational logic decomposition
13. Asynchronous spatial division multiplexing router
14. Description-level optimisation of synthesisable asynchronous circuits
15. Asynchronous Data-Driven Circuit Synthesis
16. An Asynchronous Routing Algorithm for Clos Networks
17. A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
18. Self-Timed Realization of Combinational Logic
19. M-of-N Code Decomposition for Indicating Combinational Logic
20. Computation Reduction for Statistical Analysis of the Effect of nano-CMOS Variability on Asynchronous Circuits
21. Integrated Design Environment for Reconfigurable HPC
22. A low latency wormhole router for asynchronous on-chip networks
23. LLA: A low-latency asynchronous control with applications
24. Building Asynchronous Routers with Independent Sub-Channels
25. A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
26. Heterogeneously encoded dual-bit self-timed adder
27. Teak: A Token-Flow Implementation for the Balsa Language
28. HPAP: A High Performance Control Circuit for Asynchronous Pipeline Design
29. Asynchronous Data-Driven Circuit Synthesis
30. Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks
31. Dual-Sum Single-Carry Self-Timed Adder Designs
32. Adaptive Stochastic Routing in Fault-tolerant On-chip Network
33. Forward and Backward Guarding in Early Output Logic
34. Self-Timed Full Adder Designs based on Hybrid Input Encoding
35. Power, Delay and Area Efficient Self-Timed Multiplexer and Demultiplexer Designs
36. A delay efficient robust self-timed full adder
37. Automatic Compilation of Data-Driven Circuits
38. Efficient realization of strongly indicating function blocks
39. A new design technique for weakly indicating function blocks
40. Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
41. Performance-driven syntax-directed synthesis of asynchronous processors
42. CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse
43. Speeding Up Verilog Gate-Level Simulation with Bi-Partitioning
44. Low power synthesis of XOR-XNOR intensive combinational logic
45. Synthesis of Power and Delay optimized NIG structures
46. A Framework for Distributed Simulation for Asynchronous Handshake Circuits
47. Synthesising Heterogeneously Encoded Systems
48. Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect.
49. Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
50. Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design.
51. DiSigncryption: An Integration of Agent-based Signature Delegation with Distributed Reputation Management Scheme.
52. Asynchronous On-Chip Networks.
53. Efficient Synthesis of Speed Independent Combinational Logic Circuits
54. Synthesis of Asynchronous Circuits using Early Data Validity.
55. Adding Testability to an Asynchronous Interconnect for GALS SoC.
56. Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
57. Simulation and Analysis of Synthesised Asynchronous Circuits
58. Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes
59. A Burst-Mode Oriented Back-End for the Balsa Synthesis System
60. Balsa: An Asynchronous Hardware Synthesis Language
61. Towards a Framework for the Distributed Simulation of Asynchronous Hardware
62. Synthesising an asynchronous DMA controller with Balsa
63. AMULET3: a 100 MIPS Asynchronous Embedded Processor
64. The Balsa Asynchronous Circuit Synthesis System
65. AMULET3i - an Asynchronous System-on-Chip
66. Compiling the Language Balsa to Delay Insensitive Hardware.
67. Tools for Validating Asynchronous Digital Circuits
68. Logic for Low Power Consumption in Asynchronous Circuits
69. Pitfalls in Asynchronous Design.