Investigating the Scalability of Tiled Chip Multiprocessors Using Multiple Networks.

Preethi Sam

Abstract

Abstract body.

The era of billion and more transistors on a single silicon chip has already begun and this has changed the direction of future computing towards building chip multiprocessors (CMP) systems. Nevertheless the challenges of maintaining cache coherency as well as providing scalability on CMPs is still in its initial stages of development. This thesis therefore investigates the scalability of cache coherent CMP systems.
Previous studies have shown that the single bus based cache coherent CMPs do not scale.Directory based CMPs systems provide better scalability, but have overhead in terms of the space for a full map directory as well as latency in providing for broadcasting of writes to widely shared data.
In this thesis the idea of using two separate (multiple) networks is explored for providing a combination of snoop and directory based protocols on a CMP. The cache coherency traffic is split over two separate interconnects. A limited directory based scheme with low space overhead is used over one network for handling all requests and non-broadcast based cache coherency responses. The second network is specifically used for supporting broadcast based invalidations to widely shared data. The cache coherency protocol is optimized by removing the need to generate acknowledgement messages during writes to widely shared data, as required by directory protocols. A combination of homogeneous and heterogeneous networks is implemented giving rise to two architecturally different CMP systems. The performance of both these CMP architectures is evaluated using multithreaded benchmarks. Results do confirm that the homogeneous networks based scheme is a promising design for small and medium sized CMP systems.

The thesis is available as PDF (2.2MB).