Performance Analysis of Synchronization Circuits

Zhen Zhang

Abstract

Synchronization interfaces are necessary when signals from one clock domain are imported into another. As multiple different clocks become increasingly common on chips, synchronizers also proliferate. To achieve high performance it is important that the system designer is aware of the timing characteristics of different synchronizers - which are non-deterministic by nature and can choose a design to meet their system requirements. This thesis presents a systematic method for analyzing and depicting behaviour of synchronizers and applies it to three widely recognized designs. The major contributions of this thesis are outlined as follows: A method of analyzing probabilistic behaviour of several major synchronizer performances has been proposed. Analytical expressions for predicting single-word-transfer synchronizer performance, and the average cases are derived for certain clock relationships. The cycle time dependencies are studied in detail for these synchronizers. The synchronizers are firstly modelled and abstractions of cycle time information is obtained from the analyses of the model simulation. Extension of the above analysis is made to predict synchronizer performances under burst-mode data transfer. Effect of each data transfer on the next one is fully investigated and analytical models are drawn to describe this behaviour for certain clock relationships. The resultant influence on overall synchronizer performance is then evaluated. The Synchronizer Data Cycle Analyzer (SyDCA) was developed based on these results. A new synchronizer, the three-flop synchronizer design is proposed. It originates from the analyses of the known synchronizer data cycle times in terms of their phase relationships. Preliminary investigation is carried out to analyze its performance and reliability.

The thesis is available as PDF (4.9MB).