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Dr. Matthew Horsnell

Alumni - Research Associate, APT Group.

Matt Horsnell

email: Matthew.Horsnell at the domain gmail.com
other: contact details

Post APT

I left the APT Group at the end of August 2008, and have been working at Azuro since September 2008. I still maintain an interest in the research topics listed below, as well as a new found interest in Static Timing Analysis, Clock Tree Synthesis and EDA in general. If you want to contact me you can use the above email address.

Research Topics

My most recent work has been the design and evaluation of a Hardware Transactional Memory (HTM) system that recognises objects within the hardware structure, providing an elegant solution to versioning and its associated problems of cache overflow and conflict detection. I am currently working on tile-based CMP architectures, extensions to provide highly-scalable interconnect solutions capable of supporting transactional memory, this in the embryonic stage as of January 2008, more to come shortly.

I am also interested in thread level speculation, checkpointing processors, self-validating architectures, distributed computing, and simulation. I'd welcome contact from anyone wishing to collaborate in any of these areas.

PhD Research

My PhD thesis completed in 2007 investigated the scaling limitations of the current generation of CMP architectures. In particular I investigate scaling the number of processing cores in a shared memory system upto 128 cores, faithfully modelling on-chip interconnect delays and evaluate the inefficiencies of multi-level cache hierarchies and bottle-necks associated with bus bandwidth saturation. Several architectures designs are proposed that incorporate a multi-level coherence protocol, based on semi-directory crossbar architectures, which eliminate the bus bandwidth bottlenecks. I also show that minimal extensions to the ISA, supporting locality-aware task distribution, can improve cache efficiency.
The research in my thesis was supported by a simulation tool that I developed for processor and cache architecture simulation, which has been extended and used widely in other research, including the following PhDs: Nikask, K (2008), Zhao, J (2008).

Recent Publications

J. Zhao, M. Horsnell, M. Lujan, I. Rogers, C. Kirkham, I. Watson
Adaptive Loop Tiling for a Multi-Cluster CMP
Accepted at
ICA3PP-08, to be held in Cyprus, 11th June 2008.
J. Zhao, M. Horsnell, I. Rogers, A. Dinn, C. Kirkham, I. Watson
Optimizing Chip Multiprocessor Work Distribution using Dynamic Compilation
Euro-Par , IRISA/ENS Cachan, Rennes, France, 28-31 August 2007
ISBN: 978-3-540-74465-8 , ISSN: 0302-9743 (Print) 1611-3349 (Online)
Abstract PDF(Preprint) (221K)