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On-chip timing reference for self-timed microprocessor

S. Temple, S.B. Furber


A calibratable on-chip timing reference circuit has been developed to enable a self-timed microprocessor to interface to standard off-chip memory and peripheral devices. The circuit exhibits several of the desirable properties of self-timed circuitry such as low power consumption and low electromagnetic interference (EMI). In addition, it is highly testable.

IEE Electronics Letters Vol.36 No. 11 pp.942-943
25th May 2000
ISSN 0013-5194

PDF (313K). © IEE 2000.