Prototyping a Digital Neural Network System-on-Chip using an Altera Excalibur Device

L. Ren, P. Marshall, S.B. Furber

Abstract

We present an implementation of an N-of-M code based sparse distributed memory using an Altera Excalibur device. Unlike a conventional memory, a sparse distributed memory responds not only to an exact input match, but also to any input within a specified Hamming distance of a particular input code. Therefore, it is very robust in noisy environments. The success of this prototype proves the feasibility of realising an N-of-M Kaverva memory in a system-on-a-programmable-chip, which is a good starting point for our research. In addition, it provides us with valuable design experience with the Altera Excalibur device.