Go to main content

School of Computer Science Intranet

APT research areas

Discover our main research areas

Design for Testability of an Asynchronous Adder

O. A. Petlin, C. Farnsworth, S. B. Furber


There are several different ways to implement an asynchronous adder, and each has particular testability characteristics. In this paper the stuck-at fault model is used to describe fault effects in the various adder implementations. We show that stuck-at faults on the data dependent control lines of the single-rail adder can cause both premature and delayed firings of its control outputs. The choice of single-rail, dual-rail or combined single and dual-rail (hybrid) data encoding techniques brings dDesigning Asynchronous Sequential Circuits for Random Pattern Testabilityifferent trade-offs between the testability, performance and area overhead. A case study of an asynchronous comparator demonstrates that a hybrid implementation brings a reasonable compromise between the area overhead, performance degradation and testing costs.

PDF (59K).