No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder

Wei Shao and Linda Brackenbury

Abstract

The Survivor memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or trace back approaches. In the conventional trace back implementations, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a 0.18 μm process show the new architecture saves more than 84% of the power dissipated compared with a synchronised SMU design using a low power logic family and 30% compared with a handshaking asynchronous design.

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