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A Cache Line Fill Circuit for a Micropiplined, Asynchronous Microprocessor

Rahul Mehra and J.D. Garside


In microprocessor architectures featuring on-chip cache the majority of memory read operations are satisfied without external access. There is, however, a significant penalty associated with cache misses which require off-chip accesses when the processor is stalled for some or all of the cache line refill time.

This paper investigates the magnitude of the penalties associated with different cache line fetch schemes and demonstrates the desirability of an independent, parallel line fetch mechanism. Such a mechanism for an asynchronous microprocessor is then described. This resolves some potentially complex interactions deterministically and automatically provides a non-blocking mechanism similar to those in the most sophisticated synchronous systems.

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