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CHAIN: A Delay Insensitive CHip Area INterconnect

W.J.Bainbridge, S.B.Furber


The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a globally shared bus because the high wire loads and resistances result in slow signal propagation. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in greater area requirements and still suffers from many of the same problems such as the difficulty in performing timing validation or connecting devices running from different, unrelated clocks. Furthermore, if the number and variety of macrocells embedded on a single chip is to keep growing, the interconnects used will have to be much more flexible than today's synchronous, core-specific system-buses.

We are now approaching the situation where chips will feature on-chip networks passing command and response packets between initiator and target devices. Here we describe one such network, constructed using a completely self-timed design approach that guarantees correct operation regardless of the distribution of delays in the gates and wires.