School of Computer Science Intranet
P. Capewell, I. Watson
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of resources available in many embedded systems, which typically consist of a compact RISC processor and small amounts of random access memory. Hardware support for Java execution is becoming a reality in this application area, as on-chip translation mechanisms can reduce memory requirements and increased execution speed. Power requirements can also be reduced, through a reduction in processor cycles. This paper presents an prototype architecture for hardware Java support within an ARM compatible RISC processor core, along with an asynchronous synthesised implementation. A breakdown of gate and silicon level simulation results quantifies where performance increases are achieved, providing a template for future work.