School of Computer Science Intranet
M. Lewis, L.E.M. Brackenbury
An architecture is presented for a digital signal processor (DSP) intended for use in digital mobile phones. In this application, it is necessary to balance the requirement of high processing throughput with the demand of low power for extended battery lifetime. These requirements are addressed by a multi-level power reduction strategy, involving the use of a parallel asynchronous architecture, a configurable compressed instruction set, a large register file, the use of sign-magnitude arithmetic, and a reduced support for interrupts.