Scan Testing of Asynchronous Sequential Circuits

O.A. Petlin, S.B. Furber,

Abstract

A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.

Proc. Fifth Great Lakes Symp. on VLSI, Buffalo, N.Y., USA
Mar. 16-18, 1995.