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A Chip Multi-Cluster Architecture with Locality Aware Task Distribution

Matthew Horsnell


hip MultiProcessor (CMP) architectures are fast becoming ubiquitous. Their widespread adoption has been motivated by three dominant factors; power and thermal limits have constrained higher clock frequencies, the memory wall has expedited concurrency as a means of maintaining performance, and technology advances have increased transistor budgets enabling the integration of multiple cores on a single chip. It is anticipated that a trend of increasing the number of cores with increasing transistor budgets will emerge, and that within the next decade it will be feasible to integrate up to 128 cores within a single chip architecture.

This thesis investigates the scaling limitations of current single bus CMP architectures and proposes a Chip Multi-Cluster (CMC) architecture as a feasible approach for future many-core designs. A novel cache coherence protocol and hardware support for maintaining coherence across multiple clusters is presented. Additionally, support at the hardware/software interface is provided to allow locality-aware thread creation and distribution in order to best utilise the architecture. Several possible implementations of the CMC architecture are studied through cycle accurate simulation using multithreaded benchmarks.

The thesis is available as PDF.