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Self-Timed Logic and the Design of Self-Timed Adders.

Padmanabhan, B.


The unorthodox methods usually employed for synthesising self-timed combinational logic incur substantial area overhead. A novel heuristic is proposed on the basis of set theory to considerably alleviate the problem of input state space explosion that besets function block realisations featuring several concurrent inputs. The heuristic has been implemented in Java and a system configuration in support of this heuristic is also presented. The proposed heuristic also forms the basis for realising many self-timed adders. The performance potential of various single-bit and dual-bit adder blocks, which adopt widely preferred homogeneous or heterogeneous delay-insensitive data encoding styles, are analysed on the basis of the selftimed carry-ripple adder architecture. Within this framework, hybrid adder schemes are also considered. With the intent of significantly reducing the datapath delay, the concept of redundant logic insertion has been put forward. Subsequently, to further improve the latency of dual-operand adders, self-timed section carry based carry-lookahead architectures have been proposed that outperform the basic self-timed carry-propagate adder topology. Finally, a bit-partitioning scheme for self-timed addition of multiple operands is described and a new self-timed logic compressor design is discussed. The impact of carry save adder and compressor tree structures, forming part of the input field partitions, on multi-operand addition is analysed through a case study, showing that the latter may be preferable compared to the former for self-timed multi-input addition.

The thesis is available as PDF (1.7MB).