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Memory Interconnect Management On A Chip Multiprocessor

Shufan Yang


Asynchronous Networks-on-Chip (NoCs) are emerging as an solution for man- aging global wiring resources in complex System-on-Chip (SoC) integrated cir- cuits. Asynchronous arbitration has speed and efficiency advantages that can be exploited in asynchronous NoC system designs. However, the adoption of asynchronous arbiters raises the potential problem of unfair sharing of network resources. In addition, simple asynchronous NoCs do not provide any form of service guarantee. One way to manage the unbalanced resource allocation resulting from the use of asynchronous arbiters is to increase the network capacity by adding buffers, but this is not economical since large buffers require a large silicon area. The research presented in this thesis shows how the fair service problem can be solved by controlling the traffic in the fabric to avoid saturation in critical areas and to maintain equilibrium in the allocation of resources. The research also shows how a Token-Managed Admission Control (TMAC) scheme operating at the edge of the fabric can provide service guarantees using a token mechanism to schedule packets onto the fabric. Two TMAC schemes are described: a centralised scheme and a distributed scheme. Both schemes can support Quality-of-Service (QoS) and fair service guarantees, providing latency and throughput bounds to the traffic transmitted through the fabric. Simulation results show that the proposed TMAC architecture provides time- related guarantees at low cost compared with other schemes such as virtual chan- nels or the inclusion of large buffers within the fabric. The dual-core test chip and 18-core final chip developed within the SpiNNaker project are used as case studies and show that the TMAC scheme simplifies the design of the test chip and provides a practical solution for the final chip.

The thesis is available as PDF (2.2MB).