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Low Power Viterbi Decoder Designs

Shao, Wei


This thesis represents the research work of developing new approaches for implementing Viterbi decoder designs to minimize computation complexity and power consumption. This work examines the decoding process of the Viterbi algorithm, the architecture of the Viterbi decoder, and the implementations of the basic functions. This enables the design problems to be discovered. Then a variety of low power design techniques are described and applied to the decoder design to improve its power efficiency. The new designs are tested by simulations on both software and hardware. The results give a clear view of the improvement of the modifications and enable a novel general methodology for significantly reducing complexity of decoding convolutional codes to be proposed.

The thesis is available as PDF (2.6MB).