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Synthesising Quasi-Delay-Insensitive Datapath Circuits

William B. Toms


Quasi-Delay-Insensitive circuits are more robust and amenable to reuse and verification than other circuit styles. However, their employment within VLSI synthesis systems has often been limited, as such systems often require non-standard cells or introduce delay assumptions that break the restrictions of the QDI model. This thesis presents a new combinational logic synthesis technique in which QDI/SI Boolean functions can be synthesised using a small set of standard cells. The procedure allows for implementations of functions employing arbitrary DI-codes to be generated representing a significant advance in the application of CAD techniques to QDI circuit design. An investigation of the QDI implementations of circuits within the Balsa system is undertaken and the major sources of overheads identified. Using the new combinational logic synthesis techniques, the Balsa system has been adapted to allow the synthesis of QDI circuits with arbitrary DI-encodings and channel structure. A system has been developed to analyse the data requirements of Balsa handshake circuits, and assign encodings to individual channels within designs. The use of all of the techniques introduced in this thesis are evaluated over a range of implementations of two major Balsa designs.

The thesis is available as PDF (1796KB).