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A Router for Massively-Parallel Neural Simulation.

Wu, Jian


Spiking neural network modelling is naturally suited to massively-parallel computation because of its characteristics such as simple processing components, highly-parallel communications, and small local memory requirement. However, because the real-time modelling of large-scale spiking neural networks demands very high communications efficiency, it is hard to implement on a general-purpose computer. As the feature size of transistors shrinks, a Multi-processor Systems- on-Chips (MPSoCs) with a Network-on-Chip (NoC) architecture has emerged as a promising platform for large-scale spiking neural network simulations. This dissertation presents design methodologies for a communication router in an application-specific NoC. The router realizes neural connectivity with flexibility, power-efficiency, high throughput and fault-tolerance. Three major con- tributions are:

  • A programable multicast routing infrastructure to realize neural network communications is rst presented.
  • Then a look-ahead pipeline control mechanism is implemented. It minimizes power consumption, and manages pipeline usage in a smart way, thereby maximizing the throughput.
  • An adaptive routing mechanism for multicasting is investigated to achieve system-level fault-tolerance and avoid deadlocks.

The router is a sub-system of SpiNNaker - a massively-parallel multiproces- sor platform for real-time simulations of large-scale neural networks. Based on this platform, experimental results show that the proposed router contributes significantly to both performance and energy/resource efficiency.

The thesis is available as PDF (2.8MB).