Test Interface for Micropipelined Units(TIMU)

Juan Arechabala Anaya

Abstract

Most integrated circuits designed today are synchronous. A clock signal defines the timing of all parts of the design and keeps them in step. However, there has recently been a resurgence of interest in asynchronous design, where different parts of the circuit operate at different speeds and synchronize with each other only to exchange data. As synchronous circuits form a clear majority of existing designs, asynchronous circuits must be able to interface to them, which is not always straightforward. In addition, asynchronous circuits may be problematic to test, as current chip testers are optimized for synchronous circuits.

This project has been developed with both ideas in mind. Its main aim is the design of an integrated circuit with interface and testing capabilities for asynchronous units which use a two-phase bundled data convention. The design has been developed using ES2’s 1.5um standard cells within the SOLO 2030 ECAD system.

This thesis describes the analysis, specification, design and test of this integrated circuit which is referred to by the name TIMU (Test Interface for Micropipelined Units). The chip presents a conventional 8-bit synchronous interface on one side and a two-phase bundled data interface on the other, offering buffering capabilities. As a result of its general purpose intention, flexibility has been included in the direction and width of the queues it presents. In addition it allows the loading and dumping of the whole buffer (up to 34 words on each queue) from and to the asynchronous unit.