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The Design of a Branch Target Cache for an Asynchronous Microprocessor

Suck-Heui Chung


A high performance, low power asynchronous branch target cache with several new features has been developed for the AMULET3 microprocessor at a low hardware cost. A new design for the THUMB instruction set has been implemented, together with several circuit design techniques including dynamic comparison logic, resulting in a comparison time in 1.06ns with 0.35 mm three-level metal CMOS process technology.

The thesis is available by ftp in postscript (980KB - gzipped) or pdf (6.4MB). form.