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An Analysis of Asynchronous Microprocessor Pipelines

Daranee Hormdee


This thesis reports on a comparative study of asynchronous processor pipelines. Three-stage and five-stage pipelined asynchronous implementations of a simple RISC-like architecture, the DLX, proposed by Hennessy and Patterson, were modelled and evaluated using LARD (Language for Asynchronous Research and Design). Mechanisms for solving pipeline hazards - structural, data and control hazards - that occur in asynchronous pipelined processors owing to data dependencies or resource conflict were investigated.

The mechanisms evaluated were stall, register locking, data forwarding and colour mapping. Simulation was employed to investigate the relative merits of each of these approaches and to evaluate the benefits of adapting a five-stage pipeline to asynchronous implementation for a future AMULET design.

The thesis is available by ftp in postscript (210KB compressed) or pdf (732KB) form.