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An Asynchronous DMA Controller

Chatchai Jantaraprim


An asynchronous Direct Memory Access (DMA) controller for an asynchronous microprocessor subsystem has been designed. Behavioural modelling and simulation of the DMA controller was performed using LARD, a hardware description language for asynchronous logic design. Problems in designing the DMA controller using an asynchronous logic design methodology are discussed, and solutions to these problems are presented.

The thesis is available in PDF by ftp (652KB).