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Low Power Asynchronous Digital Signal Processing

Mike Lewis


Cellular phones represent a huge and rapidly growing market. A crucial part of the design of these phones is to minimise the power consumption of the electronic circuitry, as this to a large extent controls the size and longevity of the battery. One of the major sources of power consumption within the digital components of a mobile phone is the digital signal processor (DSP) which performs many of the complex operations required to transmit and receive compressed digital speech data over a noisy radio channel.

This thesis describes an asynchronous DSP architecture called CADRE (Configurable Asynchronous DSP for Reduced Energy), which has been designed to have minimal power consumption while meeting the performance requirements of next-generation cellular phones. Design for low power requires correct decisions to be made at all levels of the design process, from the algorithmic and architectural structure down to the device technology used to fabricate individual transistors.

CADRE exploits parallelism to maintain high throughput at reduced supply voltages, with 4 parallel multiply-accumulate functional units. Execution of instructions is controlled by configuration memories located within the functional units, reducing the power overhead of instruction fetch. A large register file supports the high data rate required by the functional units, while exploiting data access patterns to minimise power consumption. Sign-magnitude number representation for data is used to minimise switching activity throughout the system, and control overhead is minimised by exploiting the typical role of the DSP as an adjunct to a microprocessor in a mobile phone system.

The use of asynchronous design techniques eliminates redundant activity due to the clock signal, and gives automatic power-down when idle, with instantaneous restart. Furthermore, elimination of the clock signal greatly reduces electromagnetic interference.

Simulation results show the benefits obtained from the different architectural features, and demonstrate CADRE's efficiency at executing complex DSP algorithms. Low-level optimisation will allow these benefits to be fully exploited, particularly when the design is scaled onto deep sub-micron process technologies.

The thesis is available by ftp in postscript (975KB) or pdf (1.5MB) form.