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Low-Power Asynchronous Multiplier Design

Yijun Liu


As process technology is scaled down and chip size is increased, tens of millions of transistors can be integrated onto a single chip. Since the sum of the power dissipation of every transistor can be significant, low-power design becomes one of the most important challenges in CMOS circuit design. Power consumption has emerged as an important design parameter in VLSI design. For some applications, such as portable and battery-operated devices, power dissipation is given a weight comparable to, or even more than, speed and area considerations.

Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers are essential subsystems not only limiting the throughput rate but affecting the power dissipation and the silicon area of digital circuits. The goal of this thesis is to reduce the power consumption of multipliers and, at the same time, to maintain their high performance with a low hardware cost.

A high-performance and low-power asynchronous ARM-compatible multiplier is proposed in this thesis. The multiplier supports 32x32 integer multiplications of both signed and unsigned operands. A novel hybrid asynchronous pipeline latch controller is used to control the datapath in order to achieve the low-power objectives. A radix-4 modified Booth’s algorithm is used in the new multiplier. Using an iterative architecture, the multiplier is processed 8 bits at a time. Furthermore, an early termination scheme speeds up the multiplication and reduces power dissipation. The multiplier consists of a total of 10700 CMOS transistors and completes a 32x32 multiplication in 12ns under typical conditions in a 0.35 micron triple metal CMOS technology. The design is very low-power and consumes only 50% of the energy per operation of its counterpart – the Amulet3 multiplier. The average power consumption is 56 mW.