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The Design of an Asynchronous Multiplier

Jianwei Liu


A high performance, low power asynchronous 32-bit multiplier with several novel features has been developed for the AMULET2 microprocessor at a low hardware cost. A new design for a 4-2 counter using differential pass-transistor logic (DTPL) has been used, together with several circuit design techniques including true single-phase clocking registers, resulting in a computation rate exceeding 200 MHz and about 58 mW power consumption with 0.6 micron triple metal CMOS process technology. The resulting cell is compact with a datapath area of only 0.32*0.71 mm2.

The thesis is available in postscript form by ftp (409kB - gzipped).