Go to main content

School of Computer Science Intranet

APT research areas

Discover our main research areas

Chip Area Network Simulation

William O. Lovett


CHAIN is a delay insensitive system-on-chip interconnect that views the challenge of connecting many functional blocks on a single chip as a networking problem.

This thesis describes a high-level simulation tool that models the workings of CHAIN in software, including automatic topology discovery/route generation and a timing model that is customisable to the level of wire and inverter delays. This simulator enables CHAIN systems-on-chip to be modelled and produces detail traffic data.

A separate tool is described that can be used to analyse this traffic data, providing information about the way in which traffic flows through the network, with which network design decisions can be made.

A background to asynchronous design methodologies, detailing its strengths and weaknesses, and why delay insensitive techniques can be usefully appplied to system-on-chip interconnects.

Common local area network topologies are described, and their properties and characteristics investigated. A number of CHAIN systems with designs based on these topologies are modelled, allowing the different topological styles to be contrasted, to discover how far parallels can be drawn between topologies in the local area and chip area network domains.

The thesis is available in pdf form by ftp (1.1MB).