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Micropipelined Cache Design Strategies for an Asynchronous Microprocessor

R. Mehra


The design of modern, pipelined, VLSI microprocessors is based almost entirely within a synchronous framework. Clock distribution in such circuits suffers from many problems. A large portion of the design effort must be devoted to overcoming these problems when fabricating synchronous designs. The throughput of synchronous pipelines is determined by the time taken for the slowest operation in any stage since this determines the maximum global clock frequency.

An asynchronous methodology may provide solutions to these short-comings by not requiring the distribution of a global clock signal. Instead circuits are constructed from small, self-timed sub-circuits within which temporal dependencies are maintained. Larger, pipelined circuits are constructed by joining these sub-components together using a simple communication protocol. This arrangement allows asynchronous pipelines to have a flexible depth and a data dependent throughput.

A block level simulator has been written that models microprocessor caches developed using a particular asynchronous methodology micropipelines. This thesis describes the development of such caches. It notes the effects of varying various cache parameters and using different strategies whilst attempting to optimise performance for a specific architecture. The target architecture is a micropipelined version of the ARM microprocessor which is currently being developed within the AMULET research group.

The thesis is available by ftp in postscript (880KB compressed) or pdf (557KB) form.