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The Design of a Low-Power Asynchronous Transform Decoder

S.S. Samra


The design of low-power asynchronous transform decoder is presented which is intended to be used as a component of an implementation of an MPEG compliant decoder. The algorithm takes into account the inherent redundancy in the average-case blocks it has to transform. The algorithms are mapped to an asynchronous hardware implementation which should significantly reduce the power consumption and silicon area compared to existing designs. This should lead to an implementation suitable for portable applications where low-power consumption is vital.