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High-Level Modelling of Micropipelines

Sun-Yen Tan


Asynchronous circuits have the potential to overcome the problems which are encountered in synchronous designs, such as clock distribution and skew. The design of asynchronous circuits has evolved using a modular approach, where a system is designed as an interconnection of modules. "Micropipelines", as expounded by Sutherland, are composed from a set of event-drivne asynchronous self-timed modules. Their operation is based on a two-phase bundled data convention. Such micropipeline design methodologies can simplify the design and reduce the design time and cost.

A micropipeline simulator is required to develop and evaluate micropipeline designs. The implementation of such a micropipeline simulator is presented in this thesis. This implementation involves the construction of Petri net models of simulated networks, the design of C++ classes for representing circuit models and Petri net models, the definition of notations for entering the simulated micropipelines and describing the simulation, and the design of the simulation procedure and evaluation rules.

Several micropipeline examples are tested to demonstrate that the simulator works correctly. Comparisons of the simulator with a standard hardware simulator, Silos II, are also presented along with an analysis of the performance of the micropipeline simulator and a discussion of the problems encountered during the implementation.

The thesis is available by ftp in postscript (286KB compressed) or pdf (911KB) form.