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Strategies for the Modelling and Simulation of Asynchronous Computer Architectures

Georgios Theodoropoulos

Abstract

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Asynchronous digital design styles promise to liberate VLSI systems from clock skew problems, offer the potential for low power and high performance and encourage a modular design philosophy which makes incremental technological migration a much easier task. The desire to exploit the potential advantages offered by asynchronous logic has recently fueled a revival of interest in asynchronous systems.

Modelling and simulation, being at the heart of digital system design, may perform a catalytic role in the quest for the realization of the potentials offered by asynchronous logic. Hence, the recurrence of interest in asynchronous design has been accompanied by an intense research activity aiming at developing techniques appropriate for modelling and simulating asynchronous systems.

Contributing to this effort, and motivated by the increasing debate regarding the potential use of CSP for this purpose, this thesis investigates the suitability of occam, a CSP-based programming language, for the modelling and simulation of complex asynchronous designs.

A modelling approach is introduced which aims to exploit the strong relationship between the semantics of occam and the structure and operation of asynchronous systems, as well as the parallelism inherent in asynchronous hardware to achieve the rapid development of asynchronous architectural simulation models, which may be executed on transputer networks to achieve high performance.

The applicability and robustness of the approach is demonstrated by employing it to construct occarm, an occam model of the AMULET1 asynchronous microprocessor.

The distributed nature of the proposed modelling approach introduces the problem of maintaining temporal precision and ensure that the causality principle is not violated.

The thesis provides a quantitative analysis regarding the timing error introduced in the model if violations of the causality principle are permitted. It then introduces the Program Driven Synchronization Protocol, a novel conservative, deadlock avoidance synchronization technique for dealing with causality problems within the framework of the proposed modelling approach.

Monitoring, debugging, termination and load balancing issues are also discussed.

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