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A single-chip multiprocessor architecture with hardware thread support

Gregory M. Wright


Multithreading and single-chip multiprocessing are two promising approaches for future microprocessor design. This thesis introduces an architecture which combines them with several novel features to support fine-grained dynamic parallelism. Hardware support is provided for locating idle processors and forking threads to them. This allows finer grained tasks to be used than is possible with a conventional software run queue, and it is shown how these features can be used by high-level Java code. Heap-allocated register windows allow fast procedure calling and flexible sharing of the register file between threads.

To connect the processors, a pipelined split-transaction cache coherence protocol has been developed. A simple enhancement to the usual load-locked/ store-conditional mechanism allows efficient spinlocks in a multithreaded environment. A possible implementation of the architecture is studied through simulation, using several simple benchmarks and two multimedia Java programs.

The thesis is available in PDF by ftp (1872KB).