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Branch Prediction Strategies for Low Power Microprocessor Design

R. York


Current interest in lower power design has arisen from two areas of application. The first is the fast emerging market for portable, battery-powered, equipment which often requires significant computing power. Secondly, for very high performance processors, there are limits to the heat that can be successfully removed from the package; this in turn puts upper limits on the number of transistors that can be fabricated in a single package. With the number of transistors on a single chip likely to rise to 100 million by the end of the decade the problems of power must be tackled now.

This thesis first examines circuit-level and architectural factors which affect power consumption, with the latter considered in more detail. Pipeline occupancy is identified as being important in many systems for both high throughput and power efficiency. Branch prediction is often used to reduce pipeline stalls; later chapters examine branch mechanisms currently in use and possible branch prediction schemes for accurate speculative execution. The architecture and design of a branch target cache for AMULET2, a low power asynchronous microprocessor, is considered. Finally possible power savings are evaluated and further schemes yielding much higher prediction accuracy are considered.

The thesis is available by ftp in postscript (545K compressed) or pdf (1.1MB) form.