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About GALAXY (see also main GALAXY website: www.galaxy-project.org)

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GALAXY Framework 7 Project: GALs interfAce for compleX digital sYstem integration

The GALAXY project builds on a technology approach in which the EU currently has world leadership, thanks to previous pan-European funding, and in which the participants are recognised centres of excellence. We propose to provide an integrated GALS (Globally Asynchronous, Locally Synchronous) design flow, together with novel Network-on-Chip capabilities, that will materially aid embedded system design for a significant class of problems. We aim to remove existing barriers to the adoption of the technology by providing an interoperability framework between the existing open and commercial CAD tools that will support development of heterogeneous systems at the different levels of abstraction. The project will evaluate the ability of the GALS approach to solve system integration issues and, by implementing a complex wireless communication system on an advanced 45nm CMOS process, explore the low EMI properties, inherent low-power features and robustness to process variability problems in nanoscale geometries.

Project goals

Development of the software needed to establish an interoperability framework between existing open and commercial tools. The measurable criteria for this will be ability for co-simulation and visualisation of heterogonous systems described using Balsa (for asynchronous part) and standard languages such as Verilog, SystemC and VHDL (for synchronous part).

Improve the current methodology for calibration and jitter control for pausible clocking in NoC applications. The measurable criteria for this will be a precision in clock calibration, possibilities for a jitter setting and complexity of suggested approach.

Demonstration of the superior properties of the GALS methodology in comparison to the state- of-the-art synchronous solutions in practice. The main parameters to confirm this are the power consumption, EMI reduction and immunity against process variation.

Demonstration of the superior properties of a GALS NoC node in comparison with a synchronous one. The main parameters to confirm this are the power consumption, speed, QoS, latency, data throughput, and needed hardware resources.

Demonstration of the superior performance of the GALS design process and design flow for medium-performance high-complexity digital systems with low-time to market. The main parameters for comparison are design time, number of design iterations, achieved clock skew, complexity and performance of the fabricated GALS and synchronous system. Those parameters must be extracted from measurements performed on implemented GALS and synchronous system with the same functionality.