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Tools Overview

Installation instructions are provided in the manual.

  • galaxy-ide / asipide

    galaxy-ide (also called asipide, AsipIDE or ASIP-IDE) is the main graphical user interface. It can be used for design entry by allowing the user to create, open, transform and save ASIP design files. For this, the main view shows a graphical representation of the design. It also serves as a front-end to launch all the other tools. For this, a tool flow window allows the user to control external tools, and an execution window provides means of interaction with these tools.

  • asip-add-cosim-comps

    Adds the required co-simulation components at the interfaces of each group of components targeting the same simulator.

  • asip-split-sim

    Splits one ASIP file into multiple ones, each of them containing only the components targeting the same simulators (1 ASIP file per simulator).

  • asip2systemc, asip2v, asip2asm, asip2bash

    These code generators read one ASIP file and generate the corresponding source code (SystemC, Verilog, ARM assembly language, bash script). In the same way as the ASIP file, the generated source code is a top-level code instantiating and linking together the various IP source codes. However, even though ASIP descriptions usually contain a hierarchy of components, the generated source codes are always flat (the hierarchy is actually flattened by asip-split-sim).

  • galaxy-wrapper-bitgen, galaxy-wrapper-map, galaxy-wrapper-ngdbuild, galaxy-wrapper-par, galaxy-wrapper-xst, galaxy-wrapper-gcc-systemc, galaxy-wrapper-arm-as, galaxy-wrapper-arm-ld

    These tools transform a file from one file format to another. This includes compilers (e.g. g++: SystemC->object file or executable), synthesisers (e.g. Xilinx XST: Verilog->netlist) and many others (e.g. netlist->Xilinx FPGA bit file). Combined in appropriate flows, they can be used to translate any HDL source code into formats that can be sent to simulators (including executable binaries, "simulated" by just executing them; e.g. SystemC simulations). The correct execution sequence of these translators is controlled by the Tool Flow System.

  • galaxy-launcher-precompiled-executable, galaxy-launcher-systemc-i386, galaxy-launcher-vcs, galaxy-launcher-icarus, galaxy-loader-arm-cpu-on-jim-s-board, galaxy-loader-virtexE-on-jim-s-board

    In the ASIP format, simulators are referred to as “Simulation Targets”, and include any tool able to execute their input code (and optionally generating a trace file). The input code can be provided in many different formats: Verilog, SystemC, but also FPGA bit files, ELF executables. In this context, simulators are therefore including software simulators, emulators, external FPGA boards, launchers of pre-compiled executable binaries, etc.