SpiNNaker Publications

Highlights

Neural systems engineering (PDF, 0.5MB)
A manifesto for the SpiNNaker project, surveying and reviewing the general level of understanding of brain function and approaches to building computer modelof the brain.

A GALS infrastructure for a massively parallel multiprocessor (PDF, 0.9MB)
A description of the Globally Asynchronous, Locally Synchronous (GALS) nature of SpiNNaker, with an overview of the asynchronous communications hardware designed to transmit neural 'spikes' between processors.

Understanding the interconnection network of SpiNNaker (PDF, 0.7MB)
Modelling and analysis of the SpiNNaker interconnect in a million-core machine, showing the suitability of the packet-switched network for large-scale spiking neural network simulation.

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware (PDF, 2.8MB)
A demonstration of SpiNNaker's ability to simulate different neural models (simultaneously, if necessary) in contrast to other neuromorphic hardware.

Power-efficient simulation of detailed cortical microcircuits on SpiNNaker (PDF, 1.7MB)
Four-chip, real-time simulation of a four-million-synapse cortical circuit, showing the extreme energy efficiency of the SpiNNaker architecture.

Hardware Architecture and Design

• Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System
• Managing a Massively-Parallel Resource-Constrained Computing Architecture
• Visualising Large-Scale Neural Network Models in Real-Time
• SpiNNaker: A Multi-Core System-on-Chip for Massively-Parallel Neural Net Simulation
• Overview of the SpiNNaker system architectur
• The Impact of Technology Scaling in the SpiNNaker Chip Multiprocessor
• An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
• Scalable Communications for a Million-Core Neural Processing Architecture
• SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip
• A Novel Programmable parallel CRC Circuit
• SpiNNaker: Effects of traffic locality and causality on the performance of the interconnection network
• A communication infrastructure for a million processor machine
• Adaptive admission control on the SpiNNaker MPSOC
• A multicast routing scheme for a universal spiking neural network architecturea
• Biologically-inspired massively-parallel architectures - computing beyond a million processors
• A token-managed admission control system for QOS provision on a best-effort GALS interconnect
• Fault-tolerant delay-insensitive inter-chip communication
• A programmable adaptive router for a GALS parallel system
• System level modelling for SpiNNaker CMP system
• An admission control system for QOS provision on a best-effort GALS interconnect
• The future of computer technology and its implications for the computer industry
• High-performance computing for systems of spiking neurons
• On-chip and inter-chip networks for modelling large-scale neural systems
• Prototyping a digital neural network system-on-chip using an altera excalibur device

Neural Simulation and System Software

• Power-efficient simulation of detailed cortical microcircuits on SpiNNaker
• Population-Based Routing in the SpiNNaker Neuromorphic Architecture
• Real Time On-Chip Implementation of Dynamical Systems with Spiking Neurons
• Event-Driven MLP Implementation on Neuromimetic Hardware
• A hierarchical configuration system for a massively parallel neural hardware platform.
• "Serial" Effects in Parallel Models of Reading
• A forecast-based STDP rule suitable for neuromorphic implementation
• Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis
• Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware
• Event-Driven SpiNNaker Simulation
• An Event-Driven Model for the SpiNNaker Virtual Synaptic Channel
• A forecast-based biologically-plausible STDP learning rule
• Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System
• Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
• Distributed Configuration of Massively-Parallel Simulation on SpiNNaker Neuromorphic Hardware
• Representing and Decoding Rank Order Codes Using Polychronization in a Network of Spiking Neurons
• Maintaining real-time synchrony on SpiNNaker
• A general-purpose model translation system for a universal neural chip
• Interfacing real-time spiking I/O with the SpiNNaker neuromimetic architecture
• STDP pattern onset learning depends on background activity
• Modeling spiking neural networks on SpiNNaker
• Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system
• Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware
• The leaky integrate-and-fire neuron: A platform for synaptic model exploration on the SpiNNaker chip
• Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware
• Scalable event-driven native parallel processing: The SpiNNaker neuromimetic system
• Efficient parallel implementation of multilayer backpropagation network on torus-connected cmps
• Event-driven configuration of a neural network CMP system over a homogeneous interconnect fabric
• Optimal connectivity in hardware-targetted MLP networks
• A universal abstract-time platform for real-time neural networks
• Virtual synaptic interconnect using an asynchronous network-on-chip
• SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor
• Efficient modelling of spiking neural networks on a scalable chip multiprocessor
• An on-chip and inter-chip communications network for the SpiNNaker massively-parallel neural net simulator

Neural Engineering

• Biologically inspired means for rank-order encoding images: A quantitative analysis
• Evaluating rank-order code performance using a biologically derived retinal model
• Maximising information recovery from rank-order codes
• Sparse distributed memory using rank-order neural codes
• A spiking neural sparse distributed memory implementation for learning and predicting temporal sequences
• An associative memory for the on-line recognition and prediction of temporal sequences
• A system for transmitting a coherent burst of activity through a network of spiking neurons
• A sparse distributed memory based upon N-of-M codes